Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

opt_demorgan: skip zero width cells #4612

Merged
merged 2 commits into from
Nov 20, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions passes/opt/opt_demorgan.cc
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,10 @@ void demorgan_worker(
return;

auto insig = sigmap(cell->getPort(ID::A));

if (GetSize(insig) < 1)
return;

log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig));
int num_inverted = 0;
for(int i=0; i<GetSize(insig); i++)
Expand Down
15 changes: 15 additions & 0 deletions tests/opt/bug4610.ys
Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
read_ilang <<EOT
autoidx 1
module \top
wire output 1 \Y
cell $reduce_or $reduce_or$rtl.v:29$20
parameter \A_SIGNED 0
parameter \A_WIDTH 0
parameter \Y_WIDTH 1
connect \A { }
connect \Y \Y
end
end
EOT

equiv_opt -assert opt_demorgan
Loading