Add Xilinx VC709 example

example/VC709/fpga/Makefile

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+# Targets
+TARGETS:=
+
+# Subdirectories
+SUBDIRS = fpga
+SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
+
+# Rules
+.PHONY: all
+all: $(SUBDIRS) $(TARGETS)
+
+.PHONY: $(SUBDIRS)
+$(SUBDIRS):
+	cd $@ && $(MAKE)
+
+.PHONY: $(SUBDIRS_CLEAN)
+$(SUBDIRS_CLEAN):
+	cd $(@:.clean=) && $(MAKE) clean
+
+.PHONY: clean
+clean: $(SUBDIRS_CLEAN)
+	-rm -rf $(TARGETS)

example/VC709/fpga/README.md

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+# Verilog Ethernet NetFPGA SUME Example Design
+
+## Introduction
+
+This example design targets the NetFPGA SUME FPGA board.
+
+The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
+will echo back any packets received.  The design will also respond correctly
+to ARP requests.  
+
+FPGA: xc7vx690tffg1761-3
+PHY: 10G BASE-R PHY IP core and internal GTH transceiver
+
+## How to build
+
+Run make to build.  Ensure that the Xilinx Vivado toolchain components are
+in PATH.  
+
+## How to test
+
+Run make program to program the NetFPGA SUME board with Vivado.  Then run
+netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234.  Any text
+entered into netcat will be echoed back after pressing enter.  
+
+

example/VC709/fpga/common/vivado.mk

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+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: clean fpga
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
+INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
+XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
+IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
+else
+  XDC_FILES_REL = $(FPGA_TOP).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(FPGA_TOP).bit
+
+vivado: $(FPGA_TOP).xpr
+	vivado $(FPGA_TOP).xpr
+
+tmpclean:
+	-rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean: tmpclean
+	-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+
+distclean: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+%.xpr: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
+	echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
+	for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
+	for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
+	for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done
+	echo "exit" >> create_project.tcl
+	vivado -nojournal -nolog -mode batch -source create_project.tcl
+
+# synthesis run
+%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
+	echo "open_project $*.xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	echo "exit" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
+	echo "open_project $*.xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "exit" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# bit file
+%.bit: %.runs/impl_1/%_routed.dcp
+	echo "open_project $*.xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $*.bit" >> generate_bit.tcl
+	echo "exit" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp $@ rev/$*_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_rev$$COUNT.$$EXT";

example/VC709/fpga/fpga.xdc

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+# XDC constraints for the Xilinx VC709
+# part: xc7vx690tffg1761-2
+
+# General configuration
+set_property CFGBVS GND                              [current_design]
+set_property CONFIG_VOLTAGE 1.8                      [current_design]
+set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1    [current_design]
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true         [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown     [current_design]
+set_property CONFIG_MODE BPI16                       [current_design]
+
+# 200 MHz system clock
+set_property -dict {LOC H19  IOSTANDARD LVDS} [get_ports clk_200mhz_p]
+set_property -dict {LOC G18  IOSTANDARD LVDS} [get_ports clk_200mhz_n]
+create_clock -period 5 -name clk_200mhz [get_ports clk_200mhz_p]
+
+# LEDs 0-7
+set_property -dict {LOC AM39 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {led[0]}]
+set_property -dict {LOC AN39 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {led[1]}]
+set_property -dict {LOC AR37 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {led[2]}]
+set_property -dict {LOC AT37 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {led[3]}]
+set_property -dict {LOC AR35 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {led[4]}]
+set_property -dict {LOC AP41 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {led[5]}]
+set_property -dict {LOC AP42 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {led[6]}]
+set_property -dict {LOC AU39 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {led[7]}]
+
+# Push buttons
+set_property -dict {LOC AU38 IOSTANDARD LVCMOS18} [get_ports {btn[0]}]
+set_property -dict {LOC AW40 IOSTANDARD LVCMOS18} [get_ports {btn[1]}]
+
+# SFP+ Interfaces
+set_property -dict {LOC AM8  } [get_ports sfp_1_rx_p]
+set_property -dict {LOC AN2  } [get_ports sfp_1_tx_p]
+set_property -dict {LOC AN6  } [get_ports sfp_2_rx_p]
+set_property -dict {LOC AP4  } [get_ports sfp_2_tx_p]
+set_property -dict {LOC AL6  } [get_ports sfp_3_rx_p]
+set_property -dict {LOC AM4  } [get_ports sfp_3_tx_p]
+set_property -dict {LOC AJ6  } [get_ports sfp_4_rx_p]
+set_property -dict {LOC AL2  } [get_ports sfp_4_tx_p]
+set_property -dict {LOC AH8  } [get_ports sfp_mgt_refclk_p]
+set_property -dict {LOC AH7  } [get_ports sfp_mgt_refclk_n]
+set_property -dict {LOC AT36 IOSTANDARD LVCMOS18} [get_ports sfp_clk_rst_n]
+set_property -dict {LOC AA42 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_mod_detect]
+set_property -dict {LOC AB42 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_mod_detect]
+set_property -dict {LOC AC39 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_3_mod_detect]
+set_property -dict {LOC AC41 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_4_mod_detect]
+set_property -dict {LOC W40  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_1_rs[0]}]
+set_property -dict {LOC Y40  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_1_rs[1]}]
+set_property -dict {LOC AB38 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_2_rs[0]}]
+set_property -dict {LOC AB39 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_2_rs[1]}]
+set_property -dict {LOC AD42 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_3_rs[0]}]
+set_property -dict {LOC AE42 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_3_rs[1]}]
+set_property -dict {LOC AE39  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_4_rs[0]}]
+set_property -dict {LOC AE40  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_4_rs[1]}]
+set_property -dict {LOC AA40 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_los]
+set_property -dict {LOC Y39  IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_los]
+set_property -dict {LOC AD38 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_3_los]
+set_property -dict {LOC AD40 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_4_los]
+set_property -dict {LOC Y42  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_1_tx_disable]
+set_property -dict {LOC AB41 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_2_tx_disable]
+set_property -dict {LOC AC38 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_3_tx_disable]
+set_property -dict {LOC AC40 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_4_tx_disable]
+set_property -dict {LOC AA39 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_tx_fault]
+set_property -dict {LOC Y38  IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_tx_fault]
+set_property -dict {LOC AA41 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_3_tx_fault]
+set_property -dict {LOC AE38 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_4_tx_fault]
+
+# I2C interface
+set_property -dict {LOC AT35 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports i2c_scl]
+set_property -dict {LOC AU32 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports i2c_sda]
+set_property -dict {LOC AY42 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports i2c_mux_reset_n]

example/VC709/fpga/fpga/Makefile

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+# FPGA settings
+FPGA_PART = xc7vx690tffg1761-2
+FPGA_TOP = fpga
+FPGA_ARCH = virtex7
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/debounce_switch.v
+SYN_FILES += rtl/i2c_master.v
+SYN_FILES += rtl/si5324_i2c_init.v
+SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
+SYN_FILES += lib/eth/rtl/eth_mac_10g.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
+SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
+SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
+SYN_FILES += lib/eth/rtl/lfsr.v
+SYN_FILES += lib/eth/rtl/eth_axis_rx.v
+SYN_FILES += lib/eth/rtl/eth_axis_tx.v
+SYN_FILES += lib/eth/rtl/udp_complete_64.v
+SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
+SYN_FILES += lib/eth/rtl/udp_64.v
+SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
+SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
+SYN_FILES += lib/eth/rtl/ip_complete_64.v
+SYN_FILES += lib/eth/rtl/ip_64.v
+SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
+SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
+SYN_FILES += lib/eth/rtl/ip_arb_mux.v
+SYN_FILES += lib/eth/rtl/arp.v
+SYN_FILES += lib/eth/rtl/arp_cache.v
+SYN_FILES += lib/eth/rtl/arp_eth_rx.v
+SYN_FILES += lib/eth/rtl/arp_eth_tx.v
+SYN_FILES += lib/eth/rtl/eth_arb_mux.v
+SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
+SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
+SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
+XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
+XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
+
+# IP
+IP_TCL_FILES = ip/ten_gig_eth_pcs_pma_0.tcl
+IP_TCL_FILES += ip/ten_gig_eth_pcs_pma_1.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+

example/VC709/fpga/ip/ten_gig_eth_pcs_pma_0.tcl

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+
+create_ip -name ten_gig_eth_pcs_pma -vendor xilinx.com -library ip -module_name ten_gig_eth_pcs_pma_0
+
+set_property -dict [list \
+    CONFIG.MDIO_Management {false} \
+    CONFIG.base_kr {BASE-R} \
+    CONFIG.SupportLevel {1} \
+    CONFIG.DClkRate {125} \
+] [get_ips ten_gig_eth_pcs_pma_0]

example/VC709/fpga/ip/ten_gig_eth_pcs_pma_1.tcl

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+
+create_ip -name ten_gig_eth_pcs_pma -vendor xilinx.com -library ip -module_name ten_gig_eth_pcs_pma_1
+
+set_property -dict [list \
+    CONFIG.MDIO_Management {false} \
+    CONFIG.base_kr {BASE-R} \
+    CONFIG.SupportLevel {0} \
+    CONFIG.DClkRate {125} \
+] [get_ips ten_gig_eth_pcs_pma_1]

example/VC709/fpga/lib/eth

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+../../../../