[GSoC] Common Verilog Generation API and Implementation in temp-sense-gen

openfasoc/generators/common/__init__.py

@@ -0,0 +1,9 @@
+"""A common module used in OpenFASOC generators.
+
+This module exports functions used in OpenFASOC generators. The following submodules and functions are exported.
+
+- `common.verilog_generation`
+	1. `generate_verilog(parameters: dict, src_dir: str, out_dir: str) -> None`: Used to generate synthesizable Verilog files (for OpenROAD flow) from source Mako-based Verilog templates.
+
+See individual function documentation for more information on a particular function.
+"""

openfasoc/generators/common/verilog_generation.py

@@ -0,0 +1,85 @@
+from mako.template import Template
+from os import path, makedirs, listdir
+
+# TODO: Find a better way to import common used defs in the future.
+__COMMON_MAKO_DEFS = '''
+<%def name="cell(name)">${cell_prefix}${name}${cell_suffix}</%def>
+'''
+
+def __mako_defs_preprocessor(input: str) -> str:
+	"""A Mako preprocessor that appens commonly used defs to the template.
+
+	Mako templates have a preprocessor argument. See https://docs.makotemplates.org/en/latest/usage.html#mako.template.Template.params.preprocessor.
+	This preprocessor adds defs commonly used in Verilog files to the template.
+	TODO: Find a better way to import common used defs in the future.
+	"""
+	return __COMMON_MAKO_DEFS + input
+
+def __generate_file(input_path: str, output_path: str, parameters: dict) -> None:
+	"""Generates a single output Verilog file from its Mako template.
+
+	Arguments:
+	- `input_path` (str): Path to the input file (Mako template) with the extension.
+	- `output_path` (str): Path to the output file location with the extension.
+	- `parameters` (dict): Dictionary of all the parameters used in the Mako template.
+	"""
+
+	# TODO: Find a better way to import common used defs in the future.
+	template = Template(filename=input_path, preprocessor=__mako_defs_preprocessor)
+
+	out_file = open(output_path, "w")
+	out_file.write(template.render(**parameters))
+
+def __generate_subdirectory(src_dir: str, out_dir: str, parameters: dict) -> None:
+	"""Generates the output Verilog files of a single subdirectory of Mako templates.
+
+	Reads Mako templates from a subdirectory (`src_dir`), generates the output files in the output directory (`out_dir`), and maintains the directory structure. i.e., templates from a subdirectory of the `src_dir` will be generated in a subdirectory in `out_dir` with the same name.
+
+	This function recursively calls itself for subdirectories.
+
+	Arguments:
+	- `src_dir` (str): Path to the source directory with Mako templates.
+	- `out_dir` (str): Path to the output directory.
+	- `parameters` (dict): Dictionary of all the parameters used in the Mako template.
+	"""
+	# generate the output directory if it doesn't exist
+	if not path.exists(out_dir):
+		makedirs(out_dir)
+
+	for filename in listdir(src_dir):
+		input_filepath = path.join(src_dir, filename)
+		output_filepath = path.join(out_dir, filename)
+
+		if path.isdir(input_filepath):
+			# if the path is a subdirectory, recursively call the function
+			__generate_subdirectory(
+				input_filepath,
+				output_filepath,
+				parameters
+			)
+		else:
+			# if the path is a fine, generate the output
+			__generate_file(
+				input_filepath,
+				output_filepath,
+				parameters
+			)
+
+def generate_verilog(
+	parameters: dict,
+	src_dir: str = "src",
+	out_dir: str = path.join("flow", "design", "src")
+) -> None:
+	"""Generates output Verilog files from source Mako templates.
+
+	Reads source Verilog files from `src_dir` and generates output Verilog files for synthesis in the OpenROAD flow.
+	The source files are Mako templates. See https://makotemplates.org for syntax and documentation.
+
+	This function maintains the source directory (`src_dir`) structure in the output directory (`out_dir`). i.e., source files from a subdirectory of the `src_dir` will be generated in a subdirectory in `out_dir` with the same name.
+
+	Arguments:
+	- `parameters` (dict): Dictionary of all the parameters used in the Mako templates. See https://makotemplates.org for documentation.
+	- `src_dir` (str): Path to the directory with the source Verilog templates.
+	- `out_dir` (str): Path to the directory in which the output will be generated.
+	"""
+	__generate_subdirectory(src_dir, out_dir, parameters)

openfasoc/generators/temp-sense-gen/Makefile

@@ -69,6 +69,7 @@ clean:
 	rm -f error_within_x.csv golden_error_opt.csv search_result.csv
 	rm -rf work
 	rm -rf tools/*.pyc tools/__pycache__/
+	rm -rf flow/design/src/tempsense
 	cd flow && make clean_all
 	cd simulations && rm -rf run
 

openfasoc/generators/temp-sense-gen/flow/design/src/.gitignore

@@ -0,0 +1 @@
+tempsense/

openfasoc/generators/temp-sense-gen/src/TEMP_ANALOG_hv.v

@@ -26,8 +26,11 @@ counter async_counter_0(
 );
 
 (* keep *)
-@@ @nf a_header_@nh(.VIN(VIN));
-SLC
-@@ @no a_buffer_0 (.A(lc_0), .nbout(lc_out));
+% for i in range(nhead):
+${header_cell} a_header_${i}(.VIN(VIN));
+% endfor
+// SLC
+${slc_cell} a_lc_0(.IN(out), .INB(outb), .VOUT(lc_0));
+${cell('buf')} a_buffer_0 (.A(lc_0), .X(lc_out));
 
 endmodule

openfasoc/generators/temp-sense-gen/src/TEMP_ANALOG_lv.v

@@ -3,16 +3,25 @@ module TEMP_ANALOG_lv (EN, OUT, OUTB);
 // inout in_vin;
  output OUT, OUTB;
  wire  n;
-@@ wire n@nn;
+
+% for i in range(ninv + 1):
+wire n${i + 1};
+% endfor
+
 wire nx1, nx2, nx3, nb1, nb2;
-@@ @na a_nand_0 ( .A(EN), .B(n@n0), .Y(n1));
-@@ @nb a_inv_@ni ( .A(n@n1), .Y(n@n2));
-@@ @ng a_inv_m1 ( .A(n@n3), .Y(nx1));
-@@ @nk a_inv_m2 ( .A(n@n4), .Y(nx2));
-@@ @nm a_inv_m3 ( .A(nx2), .Y(nx3));
-@@ @np a_buf_3 ( .A(nx3), .nbout(nb2));
-@@ @nc a_buf_0 ( .A(nx1), .nbout(nb1));
-@@ @nd a_buf_1 ( .A(nb1), .nbout(OUT));
-@@ @ne a_buf_2 ( .A(nb2), .nbout(OUTB));
+
+${cell('nand2')} a_nand_0 ( .A(EN), .B(n${ninv + 1}), .Y(n1));
+
+% for i in range(ninv):
+${cell('inv')} a_inv_${i} ( .A(n${i + 1}), .Y(n${i + 2}));
+% endfor
+
+${cell('inv')} a_inv_m1 ( .A(n${ninv + 1}), .Y(nx1));
+${cell('inv')} a_inv_m2 ( .A(n${ninv + 1}), .Y(nx2));
+${cell('inv')} a_inv_m3 ( .A(nx2), .Y(nx3));
+${cell('buf')} a_buf_3 ( .A(nx3), .X(nb2));
+${cell('buf')} a_buf_0 ( .A(nx1), .X(nb1));
+${cell('buf')} a_buf_1 ( .A(nb1), .X(OUT));
+${cell('buf')} a_buf_2 ( .A(nb2), .X(OUTB));
 
 endmodule

openfasoc/generators/temp-sense-gen/src/counter_generic.v → openfasoc/generators/temp-sense-gen/src/counter.v

@@ -28,7 +28,8 @@ module counter#
 	assign done_ref = WAKE && doneb;
 //	BUFH_X4M_A9TR	Buf_DONE(.A(done_pre), .Y(DONE));
 //	BUF_X0P4N_A10P5PP84TR_C14	Buf_DONE(.A(done_pre), .Y(DONE));
-@@ @np Buf_DONE(.A(done_pre), .nbout(DONE));
+
+	${cell('buf')} Buf_DONE(.A(done_pre), .X(DONE));
 	//assign RESET_CLK_REF = ~q1;
 
 	always @ (*) begin

openfasoc/generators/temp-sense-gen/src/tempsenseInst.v

@@ -1,4 +1,4 @@
-module tempsenseInst_error
+module ${design_name}
 (
 	input CLK_REF,
 	input RESET_COUNTERn,

openfasoc/generators/temp-sense-gen/tools/temp-sense-gen.py

@@ -2,16 +2,18 @@
 
 import json
 import os
-import re
 import shutil
 import subprocess as sp
 import sys
-import time
+import re
 
-import TEMP_netlist
 from readparamgen import args, check_search_done, designName
 from simulation import generate_runs
 
+# TODO: Find a better way to import modules from parent directory
+sys.path.append(os.path.join(os.path.dirname(__file__), '..', '..'))
+from common.verilog_generation import generate_verilog
+
 genDir = os.path.join(os.path.dirname(os.path.relpath(__file__)), "../")
 srcDir = genDir + "src/"
 flowDir = genDir + "flow/"
@@ -98,46 +100,38 @@
 print("# Verilog Generation")
 print("#----------------------------------------------------------------------")
 
+# The directory in which the output Verilog is generated
+verilog_gen_dir=os.path.join('flow', 'design', 'src', 'tempsense')
+generate_verilog(
+    parameters={
+        "design_name": designName,
+        "cell_prefix": "sky130_fd_sc_hd__" if args.platform == "sky130hd" else "sky130_fd_sc_hs__",
+        "cell_suffix": "_1",
+        "header_cell": "HEADER" if args.platform == "sky130hd" else "HEADER_hs",
+        "slc_cell": "SLC" if args.platform == "sky130hd" else "SLC_hs",
+        "ninv": ninv,
+        "nhead": nhead
+    },
+    out_dir=verilog_gen_dir
+)
 
-if args.platform == "sky130hd":
-    aux1 = "sky130_fd_sc_hd__nand2_1"
-    aux2 = "sky130_fd_sc_hd__inv_1"
-    aux3 = "sky130_fd_sc_hd__buf_1"
-    aux4 = "sky130_fd_sc_hd__buf_1"
-    aux5 = "HEADER"
-    aux6 = "SLC"
-elif args.platform == "sky130hs":
-    aux1 = "sky130_fd_sc_hs__nand2_1"
-    aux2 = "sky130_fd_sc_hs__inv_1"
-    aux3 = "sky130_fd_sc_hs__buf_1"
-    aux4 = "sky130_fd_sc_hs__buf_1"
-    aux5 = "HEADER_hs"
-    aux6 = "SLC_hs"
-
-ninv = ninv + 1
-TEMP_netlist.gen_temp_netlist(ninv, nhead, aux1, aux2, aux3, aux4, aux5, srcDir)
-
-with open(srcDir + "TEMP_ANALOG_hv.nl.v", "r") as rf:
+with open(os.path.join(verilog_gen_dir, "TEMP_ANALOG_hv.v"), "r") as rf:
     filedata = rf.read()
 header_list = re.findall("HEADER\s+(\w+)\(", filedata)
+
 with open(genDir + "blocks/sky130hd/tempsenseInst_custom_net.txt", "w") as wf:
     wf.write("r_VIN\n")
     for header_cell in header_list:
         wf.write("temp_analog_1." + header_cell + " VIN\n")
 
-with open(srcDir + "TEMP_ANALOG_lv.nl.v", "r") as rf:
+with open(os.path.join(verilog_gen_dir, "TEMP_ANALOG_lv.v"), "r") as rf:
     filedata = rf.read()
 lv_list = re.findall("\nsky130_fd_sc\w*\s+(\w+)\s+\(", filedata)
+
 with open(genDir + "blocks/sky130hd/tempsenseInst_domain_insts.txt", "w") as wf:
     for lv_cell in lv_list:
         wf.write("temp_analog_0." + lv_cell + "\n")
 
-with open(srcDir + "tempsenseInst.v", "r") as rf:
-    filedata = rf.read()
-    filedata = re.sub("module\s*(\w+)\s*\n", "module " + designName + "\n", filedata)
-with open(srcDir + "tempsenseInst.v", "w") as wf:
-    wf.write(filedata)
-
 with open(flowDir + "design/sky130hd/tempsense/config.mk", "r") as rf:
     filedata = rf.read()
     filedata = re.sub(
@@ -146,20 +140,6 @@
 with open(flowDir + "design/sky130hd/tempsense/config.mk", "w") as wf:
     wf.write(filedata)
 
-shutil.copyfile(
-    srcDir + "TEMP_ANALOG_lv.nl.v", flowDir + "design/src/tempsense/TEMP_ANALOG_lv.nl.v"
-)
-shutil.copyfile(
-    srcDir + "TEMP_ANALOG_hv.nl.v", flowDir + "design/src/tempsense/TEMP_ANALOG_hv.nl.v"
-)
-shutil.copyfile(
-    srcDir + "TEMP_AUTO_def.v", flowDir + "design/src/tempsense/TEMP_AUTO_def.v"
-)
-shutil.copyfile(
-    srcDir + "tempsenseInst.v", flowDir + "design/src/tempsense/" + designName + ".v"
-)
-shutil.copyfile(srcDir + "counter.v", flowDir + "design/src/tempsense/counter" + ".v")
-
 print("#----------------------------------------------------------------------")
 print("# Verilog Generated")
 print("#----------------------------------------------------------------------")
@@ -262,7 +242,7 @@
 print("# Generating spice netlists for the macro")
 print("#----------------------------------------------------------------------")
 
-stage_var = [int(ninv) - 1]
+stage_var = [int(ninv)]
 header_var = [int(nhead)]
 
 # make a temp list, TODO: get from JSON config

requirements.txt

@@ -7,3 +7,4 @@ nbsphinx
 cairosvg
 scipy
 ltspice
+mako