-
Notifications
You must be signed in to change notification settings - Fork 585
Issues: lowRISC/ibex
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Author
Label
Projects
Milestones
Assignee
Sort
Issues list
Implement time CSR
Component:Doc
Documentation issue
Component:RTL
RTL issue
Type:Enhancement
Feature requests, enhancements
#278
opened Sep 2, 2019 by
imphil
Make ibex_tracer_file_base a known plusarg in .core files
Component:Tool-and-Build
Tool and build system related issues
Type:Enhancement
Feature requests, enhancements
#586
opened Feb 5, 2020 by
GregAC
Docs: Use rstflattable for tables
Component:Doc
Documentation issue
Type:Enhancement
Feature requests, enhancements
#595
opened Feb 10, 2020 by
imphil
Tracer: Fix sensitivity warnings
Component:DV
Design verification (DV) or testing issue
Type:Bug
Bugs
#619
opened Feb 21, 2020 by
imphil
Feedthrough path detection
Component:Tool-and-Build
Tool and build system related issues
Type:Task
Tasks, to-do list.
#651
opened Mar 4, 2020 by
GregAC
Possible optimisations in UVM Makefile
Component:DV
Design verification (DV) or testing issue
Type:Enhancement
Feature requests, enhancements
#689
opened Mar 12, 2020 by
rswarbrick
[fpv] Write properties for top-level Ibex interface
Component:DV
Design verification (DV) or testing issue
Type:Enhancement
Feature requests, enhancements
#719
opened Mar 20, 2020 by
GregAC
DV: Use FuseSoC instead of hardcoding file list in ibex_dv.f
Component:DV
Design verification (DV) or testing issue
Type:Task
Tasks, to-do list.
#893
opened May 22, 2020 by
imphil
Add RISC-V Trace Specification-compliant interface
Component:RTL
RTL issue
Type:Enhancement
Feature requests, enhancements
#899
opened May 26, 2020 by
imphil
[rtl] Use IF skid buffer to reduce mis-predict penalty for branch prediction
Component:RTL
RTL issue
Type:Task
Tasks, to-do list.
#1097
opened Aug 27, 2020 by
GregAC
Create a Spike extension module for Ibex-specific CSRs
Component:Tool-and-Build
Tool and build system related issues
Type:Enhancement
Feature requests, enhancements
#1131
opened Oct 14, 2020 by
imphil
[rtl] Check and fix IRQ entry latency for 2-stage config
Component:RTL
RTL issue
Type:Enhancement
Feature requests, enhancements
#1332
opened Apr 13, 2021 by
vogelpi
[dv] Improve riscv_csr_test
Component:DV
Design verification (DV) or testing issue
Good First Issue
Good issue to work on for newcomers
Priority:P3
Type:Enhancement
Feature requests, enhancements
#1337
opened Apr 14, 2021 by
GregAC
4 tasks
RFC: make misa.C writeable
Component:RTL
RTL issue
Type:Enhancement
Feature requests, enhancements
Type:Question
Questions
#1353
opened May 5, 2021 by
wallento
Display configuration parameters in Verilator simulation
Component:Tool-and-Build
Tool and build system related issues
Good First Issue
Good issue to work on for newcomers
Type:Enhancement
Feature requests, enhancements
#1364
opened May 26, 2021 by
imphil
[rtl] Issues with memory and instruction fetch errors with branch prediction enabled
Component:RTL
RTL issue
Type:Bug
Bugs
#1803
opened Sep 6, 2022 by
GregAC
Clone task: [rv_core_ibex,dv] Integrate the Ibex "core_ibex" tests with dvsim
#1806
opened Sep 7, 2022 by
johngt
[dv/uvm] Detect changes in Makefile arguments
Component:DV
Design verification (DV) or testing issue
Type:Enhancement
Feature requests, enhancements
Document behaviour for insns with UNSPECIFIED behaviour while in debug mode
Component:Doc
Documentation issue
Component:DV
Design verification (DV) or testing issue
[dv] Randomize hart_id
Component:DV
Design verification (DV) or testing issue
Type:Enhancement
Feature requests, enhancements
Consider adding explicit enable for qualifying DBG_CAUSE
Component:RTL
RTL issue
Type:Enhancement
Feature requests, enhancements
Previous Next
ProTip!
no:milestone will show everything without a milestone.