Merge branch 'antmicro-52551-abc_script'

mithro · Dec 21, 2023 · d40ce30 · d40ce30
2 parents 63cc3d4 + b54f38c
commit d40ce30
Show file tree

Hide file tree

Showing 4 changed files with 56 additions and 2 deletions.
diff --git a/synthesis/BUILD b/synthesis/BUILD
@@ -22,6 +22,7 @@ package(
 )
 
 exports_files(["synth.tcl"])
+exports_files(["abc.script"])
 
 pkg_tar(
     name = "yosys",

diff --git a/synthesis/abc.script b/synthesis/abc.script
@@ -0,0 +1,45 @@
+&get -n
+&st
+&dch
+&nf
+&put
+&get -n
+&st
+&syn2
+&if -g -K 6
+&synch2
+&nf
+&put
+&get -n
+&st
+&syn2
+&if -g -K 6
+&synch2
+&nf
+&put
+&get -n
+&st
+&syn2
+&if -g -K 6
+&synch2
+&nf
+&put
+&get -n
+&st
+&syn2
+&if -g -K 6
+&synch2
+&nf
+&put
+&get -n
+&st
+&syn2
+&if -g -K 6
+&synch2
+&nf
+&put
+buffer -c
+topo
+stime -c
+upsize -c
+dnsize -c
diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl
@@ -90,13 +90,15 @@ def _synthesize_design_impl(ctx):
     default_liberty_file = ctx.attr.standard_cells[StandardCellInfo].default_corner.liberty
 
     synth_tcl = ctx.file.synth_tcl
+    abc_script = ctx.file.abc_script
 
     inputs = []
     inputs.extend(verilog_files)
     inputs.append(verilog_flist)
     inputs.append(uhdm_flist)
     inputs.extend(uhdm_files)
     inputs.append(synth_tcl)
+    inputs.append(abc_script)
     inputs.append(default_liberty_file)
 
     (tool_inputs, input_manifests) = ctx.resolve_tools(tools = [ctx.attr.yosys_tool])
@@ -125,6 +127,7 @@ def _synthesize_design_impl(ctx):
         "OUTPUT": output_file,
         "LIBERTY": default_liberty_file,
         "DONT_USE_ARGS": dont_use_args,
+        "ABC_SCRIPT": abc_script,
     }
 
     if ctx.attr.target_clock_period_pico_seconds:
@@ -265,6 +268,11 @@ synthesize_rtl = rule(
             allow_single_file = True,
             doc = "Tcl synthesis script compatible with the environment-variable API of synth.tcl",
         ),
+        "abc_script": attr.label(
+            default = Label("//synthesis:abc.script"),
+            allow_single_file = True,
+            doc = "ABC script",
+        ),
         "adder_mapping": attr.label(
             allow_single_file = True,
             doc = "Verilog file that maps yosys adder to PDK adders."

diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl
@@ -90,9 +90,9 @@ dfflibmap -liberty $liberty
 opt
 
 if { [info exists ::env(CLOCK_PERIOD) ] } {
-  abc -liberty $liberty -dff -g aig -D $::env(CLOCK_PERIOD) {*}$::env(DONT_USE_ARGS)
+  abc -liberty $liberty -dff -script $::env(ABC_SCRIPT) -g aig -D $::env(CLOCK_PERIOD) {*}$::env(DONT_USE_ARGS)
 } else {
-  abc -liberty $liberty -dff -g aig {*}$::env(DONT_USE_ARGS)
+  abc -liberty $liberty -dff -script $::env(ABC_SCRIPT) -g aig {*}$::env(DONT_USE_ARGS)
 }
 
 setundef -zero