Specify Top Module for Pure VHDL Design Exclusively During Design Elaboration #9444
Job | Run time |
---|---|
22m 25s | |
12s | |
24m 41s | |
22m 47s | |
13m 10s | |
9m 58s | |
6m 32s | |
8m 18s | |
48m 39s | |
8m 58s | |
5m 55s | |
30m 17s | |
6m 50s | |
5m 50s | |
9m 42s | |
3h 44m 14s |
Job | Run time |
---|---|
22m 25s | |
12s | |
24m 41s | |
22m 47s | |
13m 10s | |
9m 58s | |
6m 32s | |
8m 18s | |
48m 39s | |
8m 58s | |
5m 55s | |
30m 17s | |
6m 50s | |
5m 50s | |
9m 42s | |
3h 44m 14s |