Specify Top Module for Pure VHDL Design Exclusively During Design Elaboration

[awaisabbas006]

Motivate of the pull request

FOEDAG Limitation

• We don't specify top module for VHDL design during elaboration which leads to ghdl error "no top module found"

Solution

• This feature will specify the top-module for pure vhdl design.

PR Limitations

• Top module is not specified for mixed language designs (Conflicting top module name for VHDL and Verilog/SystemVerilog designs).