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Specify Top Module for Pure VHDL Design Exclusively During Design Elaboration #1672

Merged
merged 3 commits into from
Aug 14, 2024
Merged

Specify Top Module for Pure VHDL Design Exclusively During Design Elaboration #1672

merged 3 commits into from
Aug 14, 2024

Commits on Aug 12, 2024

  1. revert PR 1670

    @awaisabbas006
    awaisabbas006 committed Aug 12, 2024
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  2. fix CI

    @awaisabbas006
    awaisabbas006 committed Aug 12, 2024
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Commits on Aug 14, 2024

  1. C++ code formating

    @awaisabbas006
    awaisabbas006 committed Aug 14, 2024
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