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target/riscv: write SB address using batch #1099

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merged 1 commit into from
Jul 12, 2024
Merged

target/riscv: write SB address using batch #1099

merged 1 commit into from
Jul 12, 2024

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en-sc
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@en-sc en-sc commented Jul 3, 2024 •
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Reduces the number of JTAG queue flushes.

Requires #1081, #1082

@en-sc en-sc self-assigned this Jul 3, 2024
@en-sc en-sc force-pushed the en-sc/sb-addr-batch branch from a5c076a to d4029f5 Compare July 3, 2024 10:22
@en-sc en-sc mentioned this pull request Jul 3, 2024
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@en-sc en-sc force-pushed the en-sc/sb-addr-batch branch from d4029f5 to 8e39aa3 Compare July 4, 2024 09:23
MarekVCodasip
MarekVCodasip reviewed Jul 9, 2024
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Thanks for the patch. This is a nice improvement. I have a few suggestions, please take a look.

Also a small question, did you consider also using the improvement in sample_memory_bus_v1()? Or do you plan to implement it in a separate patch?

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@en-sc en-sc force-pushed the en-sc/sb-addr-batch branch from 8e39aa3 to 544400e Compare July 9, 2024 12:05
@en-sc en-sc requested a review from MarekVCodasip July 9, 2024 12:08
MarekVCodasip
MarekVCodasip reviewed Jul 9, 2024
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Are you leaving the sample_memory_bus_v1() for later patch then?

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en-sc commented Jul 9, 2024

Are you leaving the sample_memory_bus_v1() for later patch then?

AFAIU, sample_memory_bus_v1 is a bit different -- there is no need to override the whole address, it's enough to touch sbaddr0 to trigger the next read, so sb_write_address shouldn't be used there.

@en-sc en-sc requested a review from MarekVCodasip July 9, 2024 13:10
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Are you leaving the sample_memory_bus_v1() for later patch then?

AFAIU, sample_memory_bus_v1 is a bit different -- there is no need to override the whole address, it's enough to touch sbaddr0 to trigger the next read, so sb_write_address shouldn't be used there.

Yes, you are correct. Approving.

MarekVCodasip
MarekVCodasip previously approved these changes Jul 9, 2024
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JanMatCodasip
JanMatCodasip reviewed Jul 10, 2024
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Just one detail that I came across, otherwise this PR looks fine.

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target/riscv: write SB address using batch
6d4ad00 
Reduces the number of JTAG queue flushes.

Change-Id: Id103f5da1a3ea3177447046711e0e62a22c98c75
Signed-off-by: Evgeniy Naydanov <[email protected]>
@en-sc en-sc force-pushed the en-sc/sb-addr-batch branch from 544400e to 6d4ad00 Compare July 10, 2024 10:08
@en-sc en-sc requested a review from JanMatCodasip July 10, 2024 10:14
@en-sc en-sc merged commit 87c581a into riscv-collab:riscv Jul 12, 2024
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@en-sc en-sc deleted the en-sc/sb-addr-batch branch July 12, 2024 11:18
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@MarekVCodasip MarekVCodasip MarekVCodasip approved these changes

@JanMatCodasip JanMatCodasip JanMatCodasip approved these changes

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@en-sc @MarekVCodasip @JanMatCodasip