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Update amm2lb_verilog.j2
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stdefeber authored Sep 13, 2024
1 parent 43447e6 commit 924f9fb
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1 change: 0 additions & 1 deletion corsair/templates/amm2lb_verilog.j2
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Expand Up @@ -56,7 +56,6 @@ wire ren;

assign wstrb = byteenable;
reg ren_int;
reg {{ range_decl(config['data_width'] - 1) }} raddr_int;
{% set rst_type = config['register_reset']%}
{%- if rst_type == 'async_pos' or rst_type == 'sync_pos' %}
{% set rst_active = 1%}
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