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How does distribuf work ?
Hugues de Valon edited this page Feb 6, 2017
·
1 revision
When dispatching a signal to more than a few components, we need to take into account the transmission time. In order to optimize the fan-out and transmission loss, we need to divide the signal into a "dispatch tree".
It can take a few cycles (log_4(number of components)) for data to reach its target.
entity distribuf is
generic(
WDATA : natural := 20;
NBOUT : natural := 20;
FANOUT : natural := 20
);
port(
clk : in std_logic;
-- Input
idata : in std_logic_vector(WDATA-1 downto 0);
-- Output
odata : out std_logic_vector(WDATA*NBOUT-1 downto 0)
);
end distribuf;
-
clk
: clock signal -
idata
: data to dispatch -
odata
: data output (idata delayed for a few cycles)