How to simulate an instantiation in vivado

Créer un fichier test_nom.vhd

Utiliser le template fait avec le prof dans test_bench/test_dsp.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;

-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_dsp IS 
END test_dsp;

ARCHITECTURE behavior OF test_dsp IS
   SIGNAL clk          : std_logic;
   SIGNAL rst          : std_logic;
...
   -- cLOCK PERIOD DEfinitions
   constant clk_period : time := 1 ns;
BEGIN
      -- Instantiate the Unit Under Test (UUT)
   uut: MACC_MACRO
   generic map (
       DEVICE => "7SERIES",  -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6"
       LATENCY => 3,
       WIDTH_A => 25,
       WIDTH_B => 18,
       WIDTH_P => 48)
   PORT MAP (
       clk       => clk,
       rst       => rst
...
   );       

   -- Clock process definitions( clock with 50% duty cycle is generated here.
   clk_process :process
   begin
      clk <= '0';
      wait for clk_period/2;  --for 0.5 ns signal is '0'.
      clk <= '1';
      wait for clk_period/2;  --for next 0.5 ns signal is '1'.
   end process;
  -- Stimulus process
   stim_proc: process
   begin         
      wait for 1 ns;
      rst       <= '1';
      wait for 1 ns;
      rst       <= '0';
      a         <= B"0" & X"00_0000";
      b         <= B"00" & X"0000";
      load      <= '1';
      load_data <= X"0000_0000_0000";
...
   end process;
END;

Créer un projet vivado

make vivado &

puis suivre le clic-o-drome.

Lancer la simulation