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Recode port mapping
Hugues de Valon edited this page Feb 6, 2017
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1 revision
The vhdl structure we retrieved was kinda tricky about port mapping.
In this table, we try to explain how everything is mapped.
| First Input Fifo | Input Fifo | recode | Output Fifo |
|---|---|---|---|
| fifo_out_data | data_in | ||
| fifo_out_ack | data_in_ready | ||
| fifo_out_rdy | data_in_valid | ||
| fifo_out_ack | write_ready | ||
| fifo_out_rdy | write_enable | ||
| data_out | fifo_in_data | ||
| data_out_valid | fifo_in_ack | ||
| out_fifo_room | fifo_in_cnt |