Skip to content
This repository has been archived by the owner on Nov 4, 2024. It is now read-only.

Add support for Zfinx and Zfh extension #67

Merged
merged 18 commits into from
Aug 22, 2024

Conversation

anuani21
Copy link
Contributor

@anuani21 anuani21 commented Jul 3, 2023

Added Support for Zfh and Zfinx extensions

This PR adds

  • Added cover group format for RV32Zfh instructions.
  • Added cover group format for RV64Zfh instructions.
  • Added cover group format for RV64Zfinx instructions.
  • Introduced half width and half word in Nan boxing functionality to accommodate Zfh extensions.
  • Introduced two new flags (ZFINX and ZDINX) to aid the compilation of floating ops into integer regs.

@anuani21 anuani21 changed the title Z inx Add support for Zfinx and Zfh extension Jul 3, 2023
@anuani21
Copy link
Contributor Author

anuani21 commented Jan 3, 2024

@neelgala , -Please have your review and let us know if more information would help.

@anuani21
Copy link
Contributor Author

@neelgala , -Please have your review and let us know if more information would help.

@anuani21 anuani21 changed the base branch from master to dev March 26, 2024 06:02
@anuani21
Copy link
Contributor Author

anuani21 commented Apr 1, 2024

@allenjbaum,Can you please review this PR for approval?

@allenjbaum
Copy link
Collaborator

I'm not familiar enough with CTG to do a good job of reviewing this (though more comments would help a lot. If you've run this under riscof, and it passes tests with the correct coverage, for RV64 and RV32, with & without D/Dinx configuration, then that's the major thing. Defining coverage is what I want to see, and these extensions have more corner cases to watch out for, especially register assignments, nan-Boxing, etc.

@allenjbaum
Copy link
Collaborator

Hmm - I'm not sure we should still be referring to incoresemi license details for any of tese; that somehow seems wrong (As opposed to the icense terms that most other repos use)

@wychlw
Copy link

wychlw commented Apr 28, 2024

After some digging, I found this pr, and seems some of the ctg files need changes on check ISA, like in rv32h_fdiv.cgf#L5

      - check ISA:=regex(.*I.*F.*)

Should be

      - check ISA:=regex(.*I.*F.*Zfh.*)

The related issues are:
riscv-non-isa/riscv-arch-test#453
riscv-non-isa/riscv-arch-test#448

Maybe some changes are needed?

@UmerShahidengr
Copy link
Collaborator

UmerShahidengr commented Jul 18, 2024

@anuani21, I have made a commit to resolve the conflicts and to enable the CI. It seems like CI is failing, please take a look at it.

@anuani21
Copy link
Contributor Author

anuani21 commented Jul 18, 2024 via email

@anuani21
Copy link
Contributor Author

@UmerShahidengr, Can you please review it and commit

@UmerShahidengr
Copy link
Collaborator

@anuani21 CI is still failing. I think there is some issue in test generation for rv32 type tests.

@anuani21
Copy link
Contributor Author

anuani21 commented Aug 5, 2024

@UmerShahidengr, Can you please review it and commit??

Copy link
Collaborator

@UmerShahidengr UmerShahidengr left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Looks good to go

@UmerShahidengr UmerShahidengr merged commit 9d5e1e5 into riscv-software-src:dev Aug 22, 2024
5 checks passed
Sign up for free to subscribe to this conversation on GitHub. Already have an account? Sign in.
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

4 participants