CMR GHRD adding other peripherals

Other peripherals which the user may find useful are added and the finishing touches are done to the Platform Designer build.

Add System ID Peripheral
Add JTAG UART
Add DIP Switch IP
Add LED IP
Add Push Button IP
Assign Base Addresses and Interrupt Numbers

Add the System ID Peripheral IP

• Find the System ID Peripheral in the IP Catalog.
• Double-click it to add it to the System Contents.
• In the wizard, change the 32 bit System ID parameter to 0x1234abcd
• Click Finish.

• Rename it sys_id.
• Connect its clk port to sys_hps/h2f_user0_clock spine.
• Connect its reset port to the hps/h2f_reset spine.
• Connect its control_slave bus to the sys_hps/h2f_lw_axi_master bus.

Add jtag_uart IP

• Find the JTAG UART Intel FPGA IP in the IP Catalog.
• Double-click it to add it to the System Contents.
• Click Finish.
• Rename it jtag_uart.
• Connect its clk port to sys_hps/h2f_user0_clock spine.
• Connect its reset port to the sys_hps/h2f_reset spine.
• Connect its avalon_jtag_slave bus to the sys_hps/h2f_lw_axi_master bus.
• Connect its irq port to both sys_hps/f2h_irq0 and sys_hps/f2h_irq1 ports

Add LED IP

-Find the PIO IP in the IP Catalog.

• Double-click it to add it to the System Contents.
• Set the Width to 8 and the Direction to Output
• Click Finish.

• Rename it led_pio.
• Connect its clk port to sys_hps/h2f_user0_clock spine.
• Connect its reset port to the sys_hps/h2f_reset spine.
• Connect its s1 bus to the sys_hps/h2f_lw_axi_master bus.
• Double-Click in the Export column of external_connections and rename it led_pio

Add Push Button IP

-Find the PIO IP in the IP Catalog.

• Double-click it to add it to the System Contents.
• Set the Width to 4 and the Direction to Input
• Check the Synchronously capture box in the Edge capture register section and set the Edge Type to FALLING
• Check the Generate IRQ box and set the IRQ Type to EDGE
• Click Finish.

• Rename it button_pio.
• Connect its clk port to sys_hps/h2f_user0_clock spine.
• Connect its reset port to the sys_hps/h2f_reset spine.
• Connect its s1 bus to the sys_hps/h2f_lw_axi_master bus.
• Connect its irq port to both sys_hps/f2h_irq0 and sys_hps/f2h_irq1 ports
• Double-Click in the Export column of external_connections and rename it button_pio key

Assign Base Addresses and Interrupt Numbers

Normally, IP base addresses are assigned in Platform Designer by clicking the menu bar, selecting System -> Assign Base Addresses. BUT in this case, we need to assign the base addresses manually and lock them because the Linux device tree is expecting them to be assigned at specific addresses. To do this double-click the address in the Base column, modify it per the table below, then click the open lock icon to the left of it to lock and prevent the system from modifying the address. Note: The end address is automatically recalculated and updated by the system.

Interrupt numbers for each IP block are shown in the IRQ column inside an edit box at the vertex of the line segments. An IP block can interrupt either CPU or both. In this case, each interrupt connects to both CPUs. Modify the IRQs by clicking on the edit box in the vertex and modifying the number, insuring that both IRQs for a given IP block match.

Port	Base Address	Interrupt (if applicable)
hdmi_dmac_0	0x0009_0000	IRQ #4
axi_hdmi_tx_0	0x000a_0000	N/A
sys_id	0x0001_0000	N/A
jtag_uart	0x0001_0010	IRQ #0
led_pio	0x0001_0040	N/A
button_pio	0x0001_0020	IRQ #1

Conclude settings in Platform Designer

If there are no messages in red color (or error messages), do the following:

• Click the Generate HDL button in the bottom right of the window,
• Click Generate in the Generation window that pops up,
• Click Close in the Save System window,
• Click Close when the Generate window finishes.
• Optionally, close the Platform Designer by clicking Finish in the lower right corner of the window.

---

Next - Creating Top-Level Design
Back to Adding Display IP
Back to GHRD Top