Servo Drive Platform FPGA Architecture SINC
The SINC Filter IP implementation instantiates 1 clock generator, 2 SINC filters and 2 trip filters, but it’s easy to extend. The clock, AXI bus, and INTR are shared by all filter instantiations.
The following is a block diagram of the SINC Filter IP in the Intel FPGA
| Signal | Direction | I/O Standard | Description |
|---|---|---|---|
| SINC_D0 | input | 3.3V CMOS | Data input for SINC0 filter. Route to external pin |
| SINC_D1 | input | 3.3V CMOS | Data input for SINC1 filter. Route to external pin |
| PWM_SYNC | input | N/A | Synchronizing trigger input. Internal signal |
| SINC_MCLK | output | 3.3V CMOS | Modulator Clock output pin. Route to external pin |
| SINC0_TRIP | output | N/A | Overcurrent trip from SINC0. Internal signal |
| SINC1_TRIP | output | N/A | Overcurrent trip from SINC1. Internal signal |
| IRQ | Description |
|---|---|
| SINC0_DATA_IRQ | Interrupt generated by SINC0 filter. Indicates synchronized data output is ready to read |
| SINC1_DATA_IRQ | Interrupt generated by SINC1 filter. Indicates synchronized data output is ready to read |
If both filters run off the same clock and use the same decimation rate, the two interrupts are generated at the same time. In this case there is no need to service both. Just service one interrupt and mask the other.
| Register | R/W | Bits | Description |
|---|---|---|---|
| SINC_RESET | W | 1 | Filter and control logic reset. LSB must be asserted before starting the filter |
| SINC_MCLK_DIV | W | 16 | Sets the modulator clock frequency, MOD_FREQ: |
MOD_FREQ = PL_CLK/(2 x SINC_MCLK_DIV) |
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| For example, if PL_CLK is 100MHz and SINC_MCLK_DIV = 3 | |||
then MOD_FREQ = 100M/(2x3)=16.67MHz
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| SINC_CFG | W | 1 | SINC filter configuration |
when SINC_CFG[0] = 0 filter runs in Continuous Mode
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when SINC_CFG[0] = 1 filter runs in Flush Mode
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| SINC_EN_CNT | W | 32 | Number of PL_CLKs after PWM_SYNC before enabling the filter |
| In Continuous Mode filter is enabled only once and stays enabled | |||
| In Flush Mode filter is enabled and disabled every PWM cycle | |||
| Timer operates off the PL_CLK. For example | |||
if PL_CLK=100MHz and the filter must be enabled 10us after PWM_SYNC trigger: |
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SINC_EN_CNT = 10u x 100M = 1000 |
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| SINC_DECIMATION_RATE | W | 16 | Sets the decimation rate of the filter |
| SINC_IRQ_RATE | W | 16 | Sets the number of decimation cycles between interrupt generation |
For example, if SINC_IRQ_RATE=3 then an interrupt is generated every 3 decimation cycles |
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In Continuous Mode SINC_IRQ_RATE ≥ 1
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In Flush Mode SINC_IRQ_RATE ≥ 3
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| SINC_SCALE | W | 8 | Sets filter output scaling. Scaling is 2^SINC_SCALE
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Filter gain is SINC_DECIMATION_RATE^3 and needs to fit into a 16-bit word |
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Set SINC_SCALE so that gain ≤ 2^16. For example, if SINC_DECIMATION_RATE = 3 then SINC_SCALE = 5 because 128^3/2^5=2^16
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| SINC_ENABLE_MCLK | W | 1 | Enable modulator clock. MCLK disable when 0. MCLK enabled when 1
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| Do not enable MCLK until after PWM_SYNC is up running | |||
| SINC0_DATA_LATEST | R | 16 | 16-bit word containing the latest output from SINC0. Only valid in Continuous Mode |
| SINC0_DATA_SYNCED | R | 16 | 16-bit word containing synchronized output from SINC0. Valid in both Continuous and Flush Mode |
| SINC1_DATA_LATEST | R | 16 | 16-bit word containing the latest output from SINC1. Only valid in Continuous Mode |
| SINC1_DATA_SYNCED | R | 16 | 16-bit word containing synchronized output from SINC1. Valid in both Continuous and Flush Mode |
| SINC0_TRIP_FIL_OUT | R | 16 | Output from SINC0 trip filter |
| SINC1_TRIP_FIL_OUT | R | 16 | Output from SINC1 trip filter |
| SINC0_TRIP | R | 1 | Output form windowed statistical filter. Signal is identical to inverted interrupt signal SINC0_TRIP |
| Bit is sticky. After signal has been set, the trip filter must be reset to clear signal | |||
| SINC1_TRIP | R | 1 | Output form windowed statistical filter. Signal is identical to inverted interrupt signal SINC1_TRIP |
| Bit is sticky. After signal has been set, the trip filter must be reset to clear signal | |||
| SINC_TRIP_RESET | W | 1 | Reset of all trip filters. Must be asserted after power up as well as when resetting a trip |
| SINC_TRIP_DEC_RATE | W | 16 | Decimation rate for SINC trip filter. All trip filters use the same decimation rate |
| SINC_TRIP_EN | W | 1 | Enable of all trip signals. Notice, this signal only enables the outputs from windowed statistical filters and interrupt signals. See SINCx_TRIP. Unless SINC_TRIP_RESET is asserted, the filters are always active. |
| SINC_TRIP_LMAX | W | 16 | Maximum trip level. A filter output above this limit is detected as an overcurrent. Same level is used by all trip filters |
| SINC_TRIP_LMIN | W | 16 | Minimum trip level. A filter output below this limit is detected as an overcurrent. Same level is used by all trip filters |
| SINC_TRIP_LCNT | W | 4 | Number of overcurrents within the statistical filter window before a trip is asserted. Max value is 8. Same number is used by all trip filters |
| SINC_TRIP_LWIN | W | 4 | Window length of statistical filter. Only samples within the window are used to detect overcurrent. Max value is 8. Same number is used by all trip filters |
| REG_GLOBAL_IRQ_EN | W | 1 | SINC filter IRQ global enable. Set to 0 to disable, set to 1 to enable |
| REG_IRQ_EN | W | 2 | SINC filter individual IRQ enable. Bit 0 control SIN0 IRQ. Bit 1 controls SIN1 IRQ |
To disable set REG_IRQ_EN[x]=0
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To enable set REG_IRQ_EN[x]=1
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| REG_IRQ_ACK | W | 1 | IRQ acknowledge |
REG_IRQ_ACK[0]=1 indicates SINC0 IRQ acknowledge |
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REG_IRQ_ACK[1]=1 indicates SINC1 IRQ acknowledge |
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| REG_IRQ_PEN | R | 2 | Indicates pending IRQ |
REG_IRQ_PEN[0]=1 indicates SINC0 IRQ has been asserted |
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REG_IRQ_PEN[1]=1 indicates SINC1 IRQ has been asserted |
Impulse response is a weighted average of the input sequence. Group Delay is 1.5 Decimation Cycles.
Settling Time is 3 Decimation Cycles
The DATA_LATEST signal contains data that is output at the latest Diff Clock. The DATA_SYNCED signal contains data that is output at the latest IRQ. Output data is not synchronized to PWM_SYNC.
IRQ_RATE and MCLK are selected so that there is exactly IRQ_RATE-decimation cycles within a PWM cycle.
EN_CNT is selected so that DATA_IRQ happens 1.5 Diff Clocks after PWM_SYNC. That means clk_cnt must expire IRQ_RATE-1.5 before PWM_SYNC.
Only DATA_SYNCED is synchronized to PWM. IRQ_RATE=4 in this example.
The filter is only enabled IRQ_RATE-decimation cycles around PWM_SYNC. IRQ_RATE=3 is the minimum number of decimation cycles to obtain a valid measurement. EN_CNT is selected so that filter is enabled 1.5 decimation cycles before PWM_SYNC.
This works for any PWM frequency/decimation rate/IRQ_RATE.
The primary purpose of the SINC Overload Filter is to provide overcurrent protection without the need for any external circuitry. The SINC OL filter operates in parallel with the SINC filter from feedback (SINC FB).
When the measured signal exceeds reset limits, an Over Load Trigger is generated. This trigger is used to shut down PWM outputs and inform the application that an overcurrent has occurred. An overcurrent can happen at any time and therefore the OL filter operates with a continuous clock, even when the FB filter operates in Flush mode (discontinuous clock).
The Overload filter actually consist of two cascaded filters: A regular 3rd-order SINC (SINC3); and a windowed statistical filter. For effective overload detection, the total response time of the overload filter must be <~4us (the short-circuit time of an IGBT). The purpose of having two filters is to bring the total response time down. A response time of a few us, only allows for very low decimation rates.
SINC3 settling time is 3 decimated clock periods. For example, at fMCLK=10MHz the settling time exceeded 4us at DR=13. This means the OL filter must run with very small decimation rated in order to be fast enough.
At low DR, the output of the SINC3 is a multibit word, but it is a noisy and low-resolution signal. Basing the overload detection only on the SINC3 output would be unreliable. Adding a Windowed Statistical Filter helps in detecting overload in a predictable manner.
The statistical filter generates a trigger when X samples within a window has exceeded the upper/lower limit. For example, if 5 samples out of the last 8 samples were above the limit, a trigger is generated.
The overload trigger from the SINC OL filter is routed to the PWM timer. When a trigger is generated, the PWM timer brings all 6 PWM pins in an inactive state to protect the power inverter and/or the motor.
The PWM timer has multiple TRIPx inputs (currently 3). A trigger on any of the TRIPx inputs will shut down PWM. Typically, a system would have one TRIP signal driven by a HW detection circuit, and two trip signals driven by SINC OL filters (two phase current measurement).
When the PWM timer shuts down PWM, it generates an IRQ to notify the application a overcurrent has occurred.
The gain of the filter is DR3 and zero current (bit density of 50%) maps to a bias of DR3/2.
SINC filters for current feedback commonly have a scaling factor for the output as well as bias compensation. However, since the OL filter is running with such small decimation rates, the resolution of the output word is limited and scaling would be equivalent of throwing bits away.
For example, if DR=6 the full scale output is 216 which is less than 8-bits resolution.
Because of this, the output of the OL filter is not scaled and it is not bias compensated. When setting limits, this must be taking into account. At what current the filter trips depends on the scaling of the ADC and the size of the shunt.
Trip level example
- Assume the system uses a
20m-Ohmshunt and we want the OL filter to trip at12.5A. -
12.5Agives an ADC input voltage of250mVwhich corresponds to 89% bit density. - The Trip filter operates with
DR=8 - That means the upper trip level, LMAX, should be set to
(DR3/2 +0.89xDR3/2)=484and the lower limit should be set to(DR3/2 -0.89xDR3/2)=28. - Measurement is centered around
DR3/2 = 256
A disadvantage of the SINC trip filter is the trip level must be within the useful measurement full range. That can be a problem if you want to trip at say 2x or 3x of nominal current because it forces you to accepted poor resolution of not only the overload measurement but also of the feedback measurement path. This problem does not exist with an analog trip circuit where the trip level can be set independently of the feedback measurement.
To effectively protect the inverter motor, the OL filter must:
- Trip at a deterministic level
- Have a response time of <4us (typically, but could be shorter for some power switches)
These are contradicting requirements. 1. calls for a high decimation rate, and a long window in the statistical filter (both leading to a long response time). 2. calls for a low decimation rate and a short window in the statistical filter (both leading to undeterministic trip level). The total response time is the sum of the two filter delays (SINC filter + Statistical filter).
The response time of the filter is not deterministic. The SINC filter delay is known, but the time it takes to reach the trip level depends on the amplitude of the over current. If the amplitude of the over current is exactly at the trip level, it will take the full settling time (3 DR cycles) for the SINC filter to reach the trip level. If the amplitude of the over current is much greater than the trip level it will take less than the settling time (3 DR cycles) for the SINC filter to reach the trip level.
The input signal to the statistical filter is noisy (due to lots of left over quantization noise) so it is uncertain when the filter trips. For example, if the window is 8 samples long and we are looking for 3 of those 8 samples to be above the limit, it can take anywhere from 3 to 8 samples before a trip is asserted.
For inverter/motor protection, the worst case response time is most interesting. It is good if an overcurrent is detected faster than worst case but we cannot count on it. Worst-case response time can be calculated as the sum of the SINC filter settling time + the total statistical window length.
Through experiment, it has been found that a reasonable configuration of the OL filter is:
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SINC_TRIP_DEC_RATE = 7 -
SINC_TRIP_LWIN = 6 -
SINC_TRIP_LCNT = 3
With these settings the response time at 10MHZ modulation clock is:
3x7/10MHz + 6x7/10MHz = 6.3us
That is too slow for most applications. However, if the modulation clock is 20MHz, the response time is reduced to 3.15us which would be acceptable for some applications.
The biggest challenge with the OL filter is it’s response time. For some applications the response time is acceptable, for others it is not. Also, there is an element of unpredictability in the detection and that may be a problem for some applications.
Over current detection based on phase current measurement does not provide full inverter protection. For example, a shoot-through would go undetected. For that reason, the OL filter should be supplemented by some other protection scheme in HW. For example, an analog DC-bus overcurrent detection circuit combined with the digital overload filters is a good approach. The primary function of analog circuit protect the inverter and the primary function of the OL filter is to protect the motor (magnet/winding).
When it comes to motor protection, there is typically more time to react. That means the response time of the filter may be less of an issue than it is for inverter protection. Trip level must be within the useful measurement full scale. That can be a problem if you want to trip at say 2x or 3x of nominal current.
For this example a PWM frequency, fPWM, of 10kHz is assumed. For Continuous Mode set CFG=0
- We then need to select a MCLK and decimation rate that gives us an integer number of decimation cycles per PWM cycle.
- MCLK=PL_CLK/(2 x MCLK_DIV). Possible MCLKs are:
- MCLK_DIV=3 MCLK=16.67MHz
- MCLK_DIV=4 MCLK=12.5MHz
- MCLK_DIV=5 MCLK=10MHz
- MCLK_DIV=6 MCLK=8.33MHz
Since DR is an integer and MCLK/ fPWM must be an integer, the only MCLK options are 12.5MHz and 10MHz.
At 12.5MHz, decimation rate options are:
- DR=125 for a IRQ_RATE of 12.5MHz/(125 x 10kHz) = 10
- DR=250 for a IRQ_RATE of 12.5MHz/(250 x 10kHz) = 5
At 10MHz, decimation rate options are:
- DR=50 for a IRQ_RATE of 10MHz/(50 x 10kHz) = 20
- DR=100 for a IRQ_RATE of 10MHz/(100 x 10kHz) = 10
- DR=200 for a IRQ_RATE of 10MHz/(200 x 10kHz) = 5
- DR=250 for a IRQ_RATE of 10MHz/(250 x 10kHz) = 4
For this example we chose MCLK=12.5MHz, DR=125 and IRQ_RATE=10
- MCLK=12.5MHz, DR=125 and IRQ_RATE=10
Next step is to setup the timer that aligns the impulse response with PWM_SYNC.
We have 10 decimation cycles per PWM period. Out of these we want 1.5 decimation cycles after PWM_SYNC and 10-1.5=8.5 decimation cycles before PWM_SYNC. That means we want to shift start at the filter to 1.5 decimation cycles after PWM_SYNC.
- The alignment timer runs at PL_CLK=100MHz so EN_CNT = (1.5 x 125 / 12.5MHz) x 100MHz = 1500
- Interrupt will happen 1.5 decimation cycles after PWM_SYNC* Final step is to select a scaling factor, SCALE, so the filter gain is as close to 216 as possible
- 125^3/2^SCALE ≤ 2^16 -> SCALE=5
- Synchronized data outputs can be read from DATA_SYNCED
With Flush Mode there is freedom to set PWM frequency, modulator clock and decimation rate indecently. For the example a PWM frequency, fPWM, of 10kHz is assumed.
- For Flush Mode set CFG=1
- Set IRQ_RATE=3 which is the minimum number of decimation cycles to get a valid measurement. It’s possible to set IRQ_RATE>3 but no good reason to do so
- MCLK=PL_CLK/(2 x MCLK_DIV). Possible MCLKs are:
- MCLK_DIV=3 -> MCLK=16.67MHz
- MCLK_DIV=4 -> MCLK=12.5MHz
- MCLK_DIV=5 -> MCLK=10MHz
- MCLK_DIV=6 -> MCLK=8.33MHz
MCLK/ fPWM does not have to be an integer but for the example, we choose MCLK=12.5MHz DR can be chosen freely but best resolution is achieved with DR=2n with n an integer. For the example we chose DR=128
- MCLK=12.5MHz, DR=128 and IRQ_RATE=3
Next step is to setup the timer that aligns the impulse response with PWM_SYNC. We do a measurement in 3 decimation cycles. Out of these we want 1.5 decimation cycles after PWM_SYNC and 3 decimation cycles before PWM_SYNC. That means we want to shift start at the filter to 1.5 decimation cycles before PWM_SYNC.
- The alignment timer runs at PL_CLK=100MHz so EN_CNT = ( (1/10kHz) - (1.5 x 128 / 12.5MHz)) x 100MHz = 8464
- Interrupt will happen 1.5 decimation cycles after PWM_SYNC
- Final step is to select a scaling factor, SCALE, so the filter gain is as close to 216 as possible
- 125^3/2^SCALE ≤ 2^16 -> SCALE=5 giving optimal filter gain
- Synchronized data outputs can be read from DATA_SYNCED
To compare measurement performance of the different operating modes, a number of measurements follow. Except for mode configuration and alignment to PWM the measurements were done with the identical configuration. Any difference in results can be contributed to the effect of aligning the SINC3 impulse response correctly to PWM or not.
To eliminate any effect from the current controller, system was operated in open loop at 600rpm. The control algorithm is always executed at 10kHz but the update rate from the SINC filter will vary with settings.
In synchronized modes (continuous or flush) control algorithm update rate and SINC update rate are the same, i.e. 10kHz Data are always captured at the update rate of the SINC filter
- DECIMATION_RATE = 125
- MCLK_DIV = 4
- SCALE = 5
- EN_CNT = 5000 (enable at some point within the PWM period)
- CFG = 0
- IRQ_RATE = 6
Note: the SINC update rate here is 16.67kHz and data are captured at this rate. The control algorithm and PWM are updated at 10kHz so results are fully comparable with the measurements on the following pages
- DECIMATION_RATE = 125
- MCLK_DIV = 4
- SCALE = 5
- EN_CNT = 1500
- CFG = 0
- IRQ_RATE = 10
- DECIMATION_RATE = 125
- MCLK_DIV = 4
- SCALE = 5
- EN_CNT = 8500
- CFG = 1
- IRQ_RATE = 3
- Noise level with Continuous Mode without synchronization is ~140 cnts
- Noise level with Flush is ~7 cnts
### Comparing Cont. Mode w/o Synchronization and Flush mode at 600 RPM
- Notice how the noise amplitude varies over a fundamental period
- At times measurement point is close to the ideal at other times it is not
In it’s purest form a SINC3 filter consists of 3 integrators (accumulators) and 3 differentiators. Both accumulators and differentiators are cascaded. Accumulators are updated at the modulator clock rate and differentiators are updated at the decimated clock rate.
A pure integrator in the z-domain: 1/(1-z)^-1
The integrator has the difference equation: y[n]=u[n]+y[n-1]. To Realize an integrator on an FPGA, a DFF (Type-D Flip Flop) accumulator is commonly used:
This block has the same differential equation as the pure integrator.
Cascading 3 integrators in the z-domain: (y(z)/u(z))(1/(1-z^-1))^3 = 1/(1-3z^-2 - z^-3)
Giving the difference equation: `y[n]=u[n]+3y[n-1]-3y[n-2]+y[n-3]
Notice how a change in the input at sample n will also change the output at sample n.
Cascading 3 accumulators:
Since this is a clocked circuit, it will take several clocks for a change on the input to affect the output.
The difference equations for the cascade accumulators are:
y1[n]=u[n]+y1[n-1]
y2[n]=y1[n-1]+y2[n-1]=u[n-1]+y1[n-2]+y2[n-1]
y3[n]=y2[n-1]+y3[n-1]=u[n-2]+y1[n-3]+y2[n-2]+y3[n-1]
The figure below shows the step response of 3 cascaded integrators and 3 cascaded accumulators:
Notice how the accumulators are 2 sample delayed compared to the integrators. The integrator stage of the SINC filter is running at the modulator clock frequency, so a 2 MCLK delay has little influence on the total delay. Delay has significant impact on the filter's ability to attenuate higher frequencies. With the accumulator implementation, we are not getting the expected ENOB (effective number of bits).
To get the ideal SINC3 response the cascaded integrators are implemented as pure integrators as shown in the figure below. Note how the block consists of two parts: a clocked logic part (flip-flops) and a combinatorial part (summation). This realization requires more gates on the FPGA but it has the desired filter performance.
A pure differentiator in the z-domain is: y(z)/u(z) = 1 - z^-1
The differentiator has the difference equation y[n]=u[n]-u[n-1]
To realize a differentiator in an FPGA, a DFF (D Flip Flop) is commonly used:
The previous ADI implementation of a SINC3 cascaded the differentiator like this:
always @(posedge clk)
begin
y1 <= u - u_d;
y2 <= y1 – y1_d;
y3 <= y2 – y2_d;
u_d <= u;
y1_d <= y1;
y2_d <= y2;
end
Since everything is clocked, what you effectively get is this:
The differentiator implementation in the ADI demodulation filter has 6 clock settling time and the filter does not have the response of a SINC3. To get the desired response the differentiators is split into a clocked part and a combinatorial part. The 3 summations are combinatorial and can be put outside the clocked block:
always @ (posedge clk)
begin
u_d <= u;
y1_d <= y1;
y2_d <= y2;
end
assign y1 = u – u_d;
assign y2= y1 – y1_d;
assign y3 = y2 – y2_d;
