Servo Drive System Architecture
The implementation of Motor Control System is split between the FPGA and the ARM A9 of the SoC. Generally speaking, the most time critical functionality and peripherals, such as timers and I/O handling, are implemented on the FPGA. Application functionality such as control algorithms and system setup are implemented on the ARM A9. A top level block diagram of the system is shown in Figure 1.
The FPGA is used to implement time-critical functions and peripherals needed to control a 3-phase AC motor. Each custom peripheral is implemented as a library block (IP) and can be pulled into the design from a central IP repository. Each IP has several I/O pins that connect to the outside world and an AXI-bus (Advanced eXtensible Interface) data interface that lets the application software interact with the IP blocks. Most of the IP can generate interrupt requests to the application which is also handled over the AXI interface.
All IP is implemented with Verilog RTL code as indicated by the blue color in Figure 1 above.
The custom functions implemented on the FPGA are:
- Master Sync: a synchronization function that handles the overall timing and synchronization of the IP blocks. For example, this block resets the PWM and determines the PWM switching frequency.
- PWM Timer: a timer for generation of gate drive signals for a 3-phase power inverter. The timer outputs 6 PWM signals (2 per phase) and inserts appropriate dead-time between on/off transitions. The PWM timer also has an input signal, Trip, that shuts down all PWM signals in case of a fault.
- SINC Filters: a filter block that demodulates a sigma-delta modulated signal from an ADC. At the core of the filter block is a 3rd order SINC filter. The filter also offers fast over current monitoring for protection purposes.
- Incremental Encoder Interface: a quadrature encoder interface that translates the grey code from an incremental encoder into a multibit rotor position. The block includes filter and glitch functions for improved robustness in noisy environments.
- Hall Interface: a read of 3 commutation signals for detection of initial rotor position with 60-degree accuracy.
The Cortex A9 processor is used to implement the motor control algorithm and general application code. The Cortex A9 code interacts with the outside world through custom IP on the FPGA or fixed peripherals on the processor fabric. The main function of the Cortex A9 code is field-oriented control of a 3-phase servo motor.
The code on the Cortex A9 is implemented with either standard C-code (green blocks in Figure 1) or Model Based Design, MBD (light grey blocks in Figure 1). The Model Based Design is done in Matlab/Simulink and auto-code generation creates deployable code right from a simulation model. Model Based Design is not the focus of this demo and the details of this will not be discussed further.
The main functions implemented on the ARM Cortex A9 are:
- Device Drivers: low-level interfaces that bridge HW registers and the application code. Device drivers are used for both the custom IP and for the processor peripherals.
- Hardware Layer: setup and handling of all HW (hardware) functions. This includes scheduling and system configuration.
- Application Code: state machine and sequencing of the motor-control application
- Monitoring and Command: handles serial communication to a PC. Lets the user send commands to the system and monitor internal variables.
- SVPWM: Space Vector Modulation calculates the duty cycles for the PWM timer.
- Feedback Conditioning: scaling, calibration and filtering of feedback signals.
- Current Control: field-oriented motor-control algorithm based on d-axis and q-axis current control.
- Speed Control: motor-speed control loop.