Theory of Operation
The Motor Control Demo utilizes 4 different Demo Modes that illustrate the importance of SINC filter and control algorithm synchronization. The Demo Modes configure the system to showcases both optimal as well as non-optimal current measurement and its relation to execution of the motor control algorithm. The user can interact with the servo drive and monitor the performance of current feedback in real time. The following sections describe the details of the demo and the various demo modes. Following that, the GUI is introduced and a step by step guide to running the demo is presented.
When it comes to feedback for the motor control algorithm, the most critical part is phase-current measurement. Figure 1 shows the servo drive system consisting of a 3-phase AC motor which is driven by a switching inverter. Two resistive shunts in series with the phases together with two isolated sigma-delta ADCs are used to measure the phase currents and provide feedback for the motor control algorithm. The quality of the feedback is directly related to both dynamic and steady-state performance of the system. As control performance increases, the system becomes more and more sensitive to non-ideal effects such as timing accuracy, offset/gain errors and synchronization of multiple feedback channels. While the performance of the ADC is important, there is a high risk of introducing non-ideal effects in the rest of the feedback path as well.
The typical signal chain, when using a sigma-delta ADC, is shown in Figure 2. An analog input voltage is created by letting the phase current pass through a resistive shunt. The sigma-delta ADC converts the analog signal into 1-bit data stream and provides galvanic isolation so everything that follows the ADC is isolated from the motor phase potential. Following the converter is demodulation in the form of a filter. The filter converts the 1-bit signal into a multi-bit signal (M—bit) and brings the data update rate down through the process of decimation. While the decimation in the filter lowers the data rate, typically it is still too high to match the update rate of the control algorithm. To solve this a final down-sampling stage is added.
Sigma-delta ADCs and SINC filters are often criticized for being difficult to control in the time domain and for their lack of a defined sampling instant. When compared to a conventional ADC, with a dedicated sample-hold circuit, there is some reason for these concerns. However, there are ways to work around this. As will be shown in this section, it is crucial to synchronize the SINC filter to the rest of the system and to sample the phase current at the right instant. If this is not done correctly the resulting measurement will suffer from significant distortion.
The output from a SINC filter is not a representation of what the input to the sigma-delta ADC is at that instant. Rather, the output is a weighted average of what the input was during a windowed period in the past. This behavior is due to the filter’s impulse response. The left side of Figure 3 shows the impulse response of a SINC3 with a decimation rate of 5. The figure shows how the filter output is a weighted sum of the input sequence which gives most weight to samples at the center and less weight to samples at the beginning/end.
Before proceeding, a few basic definitions are needed. The sigma-delta ADC clock, also called the modulator clock, is referred to as fmod. The decimation rate (DR) determines the decimation frequency (fdec) and is linked to fmod as shown in equation (1.1):
The right side of Figure 3 shows the effect the impulse response has on the filter’s step response. As the step is applied, the filter output is unaffected, and it takes 3 full decimation cycles before the filter reaches steady state. Based on this, some important properties of a SINC3 filter can be stated:
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The group delay is 1.5 decimation cycles long
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The settling time is 3 decimation cycles long
These properties are very important when it comes to synchronizing the filter to the control system.
Before discussing SINC filter synchronization, the characteristics of the input signal must be defined. This, in turn, will define what the filter must be synchronized to.
Figure 4 shows a simulated phase current of a 3-phase permanent magnet motor driven by a voltage source inverter. The modulation scheme is Space Vector PWM, and the switching frequency is 10kHz. The motor is loaded to 5A peak phase current and the rotational speed is 3000rpm. With 3 pole-pairs this results in an electrical fundamental period of 6.67ms.
The phase current can be seen as two components: an averagecomponent and a switching component. For control purposes, only the average component of the current is of interest, so the switching component must be fully removed. The most common way to extract the average component is to sample the signal synchronized to the PWM waveform applied to the motor terminals. This is illustrated in Figure 5. The top signal shows the switching waveform of a phase current, the middle signal shows a high-side PWM signal for the corresponding inverter phase-leg and the lower signal shows the synchronizing signal from the PWM timer. The PWM Synchronization signal is asserted at the beginning- and the center of a PWM-cycle. For simplicity, it is assumed that all three phases run with a duty-cycle of 50% which means there is only one rising slope and one falling slope of the current. At the rising edge of PWM Synchronization signal the current assumes its average value so if the currents are sampled at exactly this instant, the switching component is fully suppressed. Effectively, the sample-hold circuit is equivalent to a filter with infinite attenuation at the switching frequency.
When this kind of sampling is applied to the waveform shown in Figure 4, the result is shown on the left of Figure 6. The right side shows a close-up of the actual phase current and the sampled current. Note how the sample-hold process completely removes the ripple.
A per-unit representation of the sampled current is used where 0A is mapped to 0.5 and full scale is 8A. This scaling is chosen for easier comparison to the sigma-delta measurements that follow. The result shown in Figure 6 is the ideal scenario with only the fundamental component left after sampling. As such, these data can be considered the benchmark to which the sigma-delta measurements will be compared.
With the ideal sample-hold ADC, it is possible to extract the fundamental component because of tight control of the sampling instant. However, sigma-delta conversion is a continuous sampling process and the ripple component will inevitably be part of the measurement.
With sigma-delta conversation there is a close link between decimation rate and signal-to-noise ratio (SNR). The higher the decimation rate is, the more effective number of bits (ENOB) of the output. The downside is as decimation rate increases the group delay also increases so the designer has to compromise between signal resolution and delay in the feedback chain. As a general rule the delay must be kept small compared to the control cycle period. For motor control, typical decimation rates fall in the range of 128 to 256 which provides a good compromise between SNR and group delay.
Suppose the phase current shown in Figure 4 is measured with a sigma-delta ADC clocked at 20MHz and the data stream is demodulated by a SINC3 using a decimation rate of 256. The result is shown in Figure 7 A.
The fundamental component of the phase current is obvious, but the measured signal is very noisy when compared to the ideal sampling shown in Figure 6 A. So while the ADC and SINC filter by themselves provide impressive ENOB numbers, the quality of the feedback signal is quite poor. The reason for this can be seen in Figure 7 (B) which shows a close-up of the SINC filter output and the actual phase current. Notice how the 10kHz switching component of the phase current is phase shifted but hardly attenuated by the SINC filter. Now, suppose the motor control algorithm is executed once per PWM period and that the latest SINC filter output is read at the beginning of the period. Effectively the SINC filter output is down sampled to match the update rate of the control algorithm. The down sampling and resulting signal are shown as Sampled SINC Output in Figure 7 (B). When a full fundamental period is filtered and sampled at the PWM rate, the result is shown in Figure 8 (A).
It is clear the phase current measurement is highly distorted and would lead to poor control performance. Increased torque ripple and a need to reduce bandwidth of the current control loop should be expected. If the measurement in Figure 8 A is subtracted from the ideal measurement (Figure 5 A) the error is obtained, see Figure 8 B. The error is approximately 7% of the full scale signal which is very far from matching the expected 14 ENOB.
The example demonstrates a very common operating mode of sigma-delta based current measurement and it has led designers to conclude sigma-delta ADCs are unsuited for motor drives. However, the example does not demonstrate the poor performance of the ADC itself. Rather, it demonstrates poor performance of the remaining signal chain because it is not properly set up for phase current measurement.
The ADC samples the input signal at several mega-hertz (typically 10-20MHz), and with a decimation rate of 256 the SINC filter effectively removes the modulation noise. With such a high sampling rate the ripple component of the phase current is present in the filter output and that that can become a problem in the down sampling stage of the signal chain, see Figure 2. If the ripple component is not sufficiently attenuated, and the motor control algorithm consumes current feedback at the PWM rate, the result is aliasing due to down-sampling as illustrated by the example above.
To avoid aliasing the signal must be free of energy above half the down-sampling frequency, as per standard sampling theory. In the example the signal was down-sampled to 10kHz so any noise at 5kHz or higher will fold into the measurement. As shown, there was plenty of 10kHz switching noise left in the signal after the SINC filter. One option to attenuate the 10kHz noise is to increase the decimation rate but doing so would result in unacceptable long group delay. A different approach is needed.
The main problem with the approach discussed in the previous section is illustrated in Figure 9. The output from the SINC filter is read at some instant uncorrelated to the switching component of the phase current. When the output is read, the filter delivers a weighted average of the input signal according to the impulse response. Sometimes this weighted average spans the low point of the switching waveform and sometimes it spans the highpoint. As a result, the signal used as feedback contains significant random noise with frequencies from 0Hz to half the PWM frequency.
A sigma-delta ADC samples continuously and the SINC filter outputs multiple measurements per PWM cycle (typically 10-20). Since each measurement spans 3 decimation cycles the impulses responses overlap. For simplification, only 3 of these measurement/impulses responses are shown Figure 9.
The source of the problem is that the impulse response is not locked to the switching component of current which in turn is locked to PWM. The solution is to select the decimation rate so that there are a fixed integer number of decimation cycles per PWM period. For example, with a PWM frequency of 10kHz, a modulator clock of 20MHz and a decimation rate of 200, there is exactly 10 decimation cycles per PWM period. With a fixed number of decimation cycles per PWM period, the impulse response is always locked to PWM and the measurement used for feedback is captured at the same point within the PWM cycle.
However, not only does the impulse response need to be locked to PWM. It is also very important to correctly align the phase of the impulse response with respect to PWM. With the center of the impulse response located around the beginning or around the center of a PWM period, where the phase current is exactly at its average value, the harmonic error is eliminated. Around these points the switching waveform is symmetrical, so by having an equal number of measurement points on either side, the ripple component averages average out.
Figure 10 shows the impulse response centered at the beginning of a switching period. Around this point the switching waveform is symmetrical so by having an equal number of measurement points on either side, the ripple component averages out to zero around this point.
With the impulse response locked and centered around the instant of average current, the resulting measurement is shown in Figure 11 A and the measurement error is shown in Figure 11 B. Similar to an ideally sampled measurement the signal is free of both white noise and gain error.
The presented results show the quality of a sigma-delta measurement relies on much more than just the decimation rate. The common belief that increasing the decimation rate will result in higher effective number of bits is only true in the absence of aliasing. Controlling the filter update rate and phase with respect to the input signal is much more important than the decimation rate. As an example, compare Figure 8, which was based on a decimation rate of 256, and Figure 11, which was based on a decimation rate of 200. Lowering the decimation rate improved the measurement significantly.
An alias-free sigma-delta measurement is possible by correct alignment of the SINC filter impulse response to PMW. While the method is straight forward it is difficult, and in many cases impossible, to find a system configuration that gives the desired result. To illustrate this, assume the SINC filter and the PWM block shares a common system clock source that runs at fsys. The modulator clock, fmclk, is then determined by equation (1.2).
Where Dmclk is the clock divider for the modulator clock. Similarly, the PWM frequency, fpwm, is determined by equation (1.3).
Where Dpwm is the clock divider determining the PWM frequency. Finally, the decimation rate (data rate) from the SINC filter is given by equation (1.4).
Where Ddec is the clock divider for the decimated clock. By:
Where N is an integer. By combining , and :
Clearly, only a limited selection of clock scalers, Dx, satisfy . Furthermore, most often there are tight restrictions on how the clock scalers can be selected. For example, a system may be required to run at a certain PWM frequency (say 10kHz) or use a certain modulator clock (say 20MHz). Another complication is the limited number of options when it comes to selecting the modulator clock. For example, if fsys is 100MHz the only reasonable choices for Dmclk falls in a limited range of integers 5 to 10 (20MHz down to 10MHz).
Given all these restrictions it is very difficult, if not impossible, to find clock scales that give the desired alignment between impulse response and PWM. What typically happens is the user is forced to select clock scalers that satisfy the equation rather than selecting clock scales that results in desired PWM frequency, modulator clock and signal-to-noise ratio. Also, if one of the frequencies changes over time it becomes impossible to find a valid configuration. This is quite common in multi-axes systems where a single motion controller synchronizes multiple motor controllers in a network.
While the alignment scheme gives excellent measurement performance it can prove to be impractical. In the following section a new type of SINC filter is presented. The filter offers optimum measurement performance and at the same time allows the user to select all clock dividers independently.
A traditional 3rd-order SINC filter is shown in Figure 12. The filter generates the modulator clock to the ADC by scaling the system clock, and in return the ADC generates a 1-bit data stream to the filter. The filter function itself consist of 3 cascaded integrators, 1/(1-z-1), clocked at the same rate as the modulator, and 3 cascaded differentiators, 1-z-1, clocked at the decimated clock.
The SINC filter and ADC are operated by continuously applying a clock to both. As a result, the filter outputs data continuously at a fixed rate determined by the decimated clock. The data rate from the filter is typically higher than the update rate of the motor control algorithm, so a number of the filter outputs are rejected. Only when the impulse response is centered around the ideal measurement is the output captured and used as feedback.
With space-vector modulation the phase current only assumes its average value two times per PWM period. Following this, there are only two possible alias-free SINC data output per PWM cycle, so there really is no need to let the filter run continuously. It is actually sufficient to only enable the measurement when the feedback is needed and then disable at all other times. In other words, the measurement operates in an on/off mode not unlike a conventional ADC.
A problem with the on/off mode of operation is the modulator clock and filter clock are derived from the same system clock. That means both the filter and the ADC operate in an on/off mode, which is not recommended because it will result in reduced performance. The reason is the modulator in the ADC is a higher order system with a certain settling time and damping. So when first applying a clock to the ADC, the modulator needs to settle before the output bit-stream can be trusted. To solve these problems a new filter structure is proposed, see Figure 13.
As the standard SINC filter, the core consists of 3 cascaded integrators and 3 cascaded differentiators. However, the filter has several features that allow for new operating modes. Firstly, the filter has a new Clock Generator function that separates the modulator clock from the integrator clock. That makes it possible to continuously clock the ADC but only enable the integrator clock when obtaining a measurement. Secondly, the filter has a new Filter Control function. With reference to a Synchronization Pulse the control block handles all timing and trigging needed to operate the filter. The primary function of the filter controller is flushing the filter which involves initializing all filter states and timers, filter ahead of starting a new measurement, as well as enable/disable the integrator clock at the right instances. Finally, the filter has a new Buffer and Interrupt Control unit which sorts through the output data and captures the correct measurement. The Buffer and Interrupt unit also notifies the motor control application by interrupt when a new measurement is ready to be consumed. The timing diagram in Figure 14 shows how the filter operates.
To start a measurement, a Synchronization Pulse (Sync Pulse) is applied to the Filter Controller. Typically, this pulse indicates the start of a new PWM cycle. The Sync Pulse starts a timer which is configured to expire exactly 1.5 Decimation cycles before the desired measurement point. At this point, the Integrator Clock and Decimated Clock are enabled and the filtering process begins. After 3 Decimation Cycles (settling time of a 3rd order SINC filter) the Buffer and Interrupt Controller captures the Data Output and asserts the Interrupt. In the figure, notice how the measurement is centered around the Synchronization Pulse. The sequence repeats itself at the next Synchronization Pulse.
The proposed SINC filter solves the problem of synchronization of a conventional SINC filter. The filter and its operating mode do not make any assumptions about PWM frequency, modulator clock or decimation rate. It works equally well with all system configuration and even if the PWM frequency varies over time. Since the filter is effectively reset for every measurement it is also insensitive to drift between the clocks.
The demo system contains 4 preconfigured operating modes (Mode 1 - Mode 4) which the user can preselect from the GUI. The demo modes highlight the phase current measurement techniques discussed above and lets the user monitor the results in real time through plotting window in the GUI.
While the control system supports closed-loop field-oriented control, some Modes configure the system to run in open-loop control (no speed- or current control). A closed current loop is sensitive to measurement noise and the noise will couple through the current loop. By operating in open loop, any effects from the current controllers are eliminated which makes it possible to compare results directly.
For phase current measurement the system has 2 isolated sigma-delta ADC (ADuM7701) followed by two 3rd order SINC filters. The SINC filters are implemented using the design recommendation discussed above including the flushing SINC mode of operation. For comparison, the Modes illustrate both the traditional continuously operating filter as well as the flushing filter.
Except for alignment to PWM, the Modes configure the system with identical parameters, including decimation rate which is set to 125 in all modes. Any difference in the measurement results can therefore be contributed to the effect of aligning the SINC3 impulse response correctly to PWM or not. The control algorithm is executed at 10kHz and the modulator clock is 12.5MHz.
The details and expected results of each Mode are listed below.
In Mode 1 the system operates with full closed-loop field-oriented control. Mode 1 is the only close-loop mode and as such not comparable to Mode 2, Mode 3 and Mode 4. It is, however, the mode that offers best control performance and demonstrates the capability of the system. A block diagram of the closed loop control algorithm is shown in Figure 15.
The voltage fed Inverter drives a three-phase ac motor under the control of a PWM modulator. Utilizing Space Vector Modulation (SVPWM), the inverter produces fixed frequency variable duty cycle waveforms, vu, vv and vw, modulated with the target motor voltage and frequency. The motor windings filter the high frequency components, and motor current is at the modulation fundamental frequency with some residual ripple.
As feedback for the control algorithm, the motor currents iv and iw are measured with sigma-delta ADC and the rotor position qr is measured with an incremental encoder. The 3 phase currents are projected on to a 2-phase reference frame using the Clarke transform, which produces ia and ib. Finally, Reverse Park transform is used to project the phase currents onto a rotating reference frame locked to the rotor position. Hereby the feedback for the current controller, id and iq, are obtained. id is aligned with the flux of the permanent magnet on the rotor of the motor and iq is the torque producing component of the current.
The system has 3 control loops: An outer Velocity Loop and two inner Current Loops. The Velocity Loop controls the motor speed wr by generating a torque command Iq* for the current loop. The Current Loops control the d- and q components of the phase currents by generating voltage references, vd* and vq* for the motor. In this system, the reference for the d-axes current controller, Id*, is always set 0, meaning no field-weakening.
The reference voltages, vd* and vq*, are aligned to the rotor position using Forward Park transformation which produces va and vb. These 2-phase AC quantities are transformed into 3 phase quantities using Forward Clark Transform which produces reference voltages, vu, vv and vw, for the Power Inverter.
The PWM modulator provides synchronizing triggers for the whole system, including SINC filter, Encoder interface, and execution of the control algorithm. The update rate of the control system is 10kHz. However, the speed loop is down sampled to an update rate of 10kHz.
The current loops are tuned to a bandwidth of 1kHz. Figure 16 shows measured step responses of the iq current control loop.
Control performance of the speed loop is shown in Figure 17. Note how the speed reference is rate limited to avoid unrealistic acceleration rates.
In Mode 1, the system operates with optimum settings and a flushing SINC3 filter correctly aligned to PWM. A timing diagram of the SINC filter operating mode is shown in Figure 18.
In Mode 2 the SINC filter and current feedback operates with optimum settings and a flushing SINC3 filter exactly like Mode 1, see Figure 18. However, in Mode 2 the control algorithm is open loop, meaning the control algorithm does not utilize any feedback (phase current and rotor angle). The algorithm simply applies 3 AC voltages to the motor with a frequency determined by the speed reference and an amplitude proportional to the speed reference.
Control performance in open loop is quite poor and especially at low speed the motor is not likely to follow the speed reference. In open loop it is recommended to run the motor at ~250rpm which gives stable operation and reasonable current amplitudes. In open loop the speed reference is limited to 500rpm.
By operating in open loop, any effects from the current controllers are eliminated which makes it possible to compare results from the different operating Modes directly.
Figure 19 shows the expected results when operating in Mode 2. The left side of Figure 19, shows the phase current measurements when the motor is stopped but the power inverter is switching with a duty-cycle of 50% on all phases (0 rpm). In this operating mode the measurement shows the noise level of the measurement. The right side of Figure 19, shows the phase currents when the motor is running open-loop at 250RPM.
The filter is configured to only run for 3 decimation cycles around the ideal measurement point but otherwise disabled. The result is optimal performance of the current feedback system.
In Mode 3 the motor control algorithm runs open loop and the SINC filter runs continuously. The SINC filter impulse response is locked and correctly aligned to PWM. With the center of the impulse response located around the beginning of a PWM period, where the phase current is exactly at its average value, the harmonic error is eliminated.
A timing diagram of Mode 3 is shown in Figure 20. In this example there is an integer number of decimation cycles per PWM period (4) and the impulse response is aligned with the ideal measurement point. Note that once the filter has been started, it runs continuously.
Figure 21 shows measurement results when operating in Mode 3. The results in Figure 21 are directly comparable with the results in Figure 19. As expected, the measurement performance is identical.
In Mode 4 the motor control algorithm is open loop and the SINC filter runs continuously. In contrast to Mode 3, where the SINC filter impulse response was correctly aligned to PWM, the SINC filter is unaligned to PMW in Mode 4. There is a non-integer number of decimation cycles per PWM cycle and the phase between SINC filter impulse response and PWM drift over time.
A timing diagram of Mode 4 is shown in Figure 22. In this example there is 4 decimation cycles per PWM period. Note that once the filter has been started, it runs continuously.
Figure 23 shows measurement results when the SINC filter impulse response if unaligned to PWM (Mode 4). When comparing the results in Figure 23 to the results in Figure 19 and Figure 21, it becomes clear how important proper configuration and operation of the SINC filter is.
