Servo Drive Platform FPGA Architecture PWM

PWM IP Features

• PWM for 3-phase full bridge inverter​
• Synchronization from Master Sync Block​
• PWM generation independent of timer period​
  • No internal SYNC​
• Asymmetric dead time​
• Dead time insertion in all operation modes​
  • Clamp and over modulation supported​
• Active low level gate signals (easily changed)​
• Double-buffered registers​
  • Duty-cycles​
  • Dead time​
• Synchronous ITRIP protection​
• Single/double update mode (through ext. sync)​
• Dependent HS and LS control​

PWM Implementation

• Sync generation is split from the actual PWM timer
• AXI (Advanced eXtensible Interface) for interaction with the software application on embedded Arm Cortex-A9 HPS (Hard Processor System)
• Interrupts go through AXI as well

PWM IP I/O

Signal	Direction	I/O Standard	Description
ITRIP	input	3.3V CMOS single ended	Active-low over-current trip from external analog circuit. Route to external pin
SINC0_TRIP	input	Internal signal	Active-low over-current trip from SINC0
SINC1_TRIP	input	Internal signal	Active-low over-current trip from SINC1
MSTR_SYNC	input	n/a	Not supported in current version
pwm_sync	output	Internal signal	PWM synchronization signal.​ Currently only used internally but could be routed to external pin​
PWM_AL_out	output	3.3V CMOS single ended	PWM Phase A Low-side gate-drive signal. Route to external pin
PWM_AH_out	output	3.3V CMOS single ended	PWM Phase A High-side gate-drive signal. Route to external pin
PWM_BL_out	output	3.3V CMOS single ended	PWM Phase B Low-side gate-drive signal. Route to external pin
PWM CL_out	output	3.3V CMOS single ended	PWM Phase C Low-side gate-drive signal. Route to external pin
PWM CH_out	output	3.3V CMOS single ended	PWM Phase C High-side gate-drive signal. Route to external pin
pwm_led_pin	output	3.3V CMOS single ended	Toggling signal to flash LED. Indicates PMW IP is alive. Route to external pin
PWM_EN_PIN	output	3.3V CMOS single ended	Active-high, gate-driver enable. Route to external pin

Interrupts

IRQ	Description
PWM_SYNC_IRQ	Generated every time the PWM timer resets. Indicates the start of a new PWM period. Note, this signal is also used to trigger/synchronize various I/Os in the system.​
PWM_TRIP_IRQ	Generated when a trip has occurred. Trip is a negative going edge on either ITRIP, SINC0_TRIP or SINC1_TRIP.​ At trip the gate drive signals are put into the inactive OFF state

PWM Registers

Register	R/W	Bits	Description
RESET_SYNC	W	1	Sync-generator reset. assert->deassert LSB of register before starting sync generator and PWM
ENABLE_SYNC	W	1	Sync-generator enable. LSB of resgister must be asserted before enabling PWM
RESET_PWM	W	1	PWM block reset. assert->deassert Register's LSB before enabling PWM
ENABLE_PWM	W	1	PWM enable. Register's LSB must be asserted to enable PWM
MASTER_CNT_MAX	W	16	Sets PWM sync frequency and PWM frequency.
			f_pwm = PL_CLK/PWM_CNY_MAX
			PL_CLK is 100MHz in current configuration
DEAD_TIME	W	16	Sets the deadtime between high/low side turn-on/turn-off​
			t_deadtime=DEAD_TIME/PL_CLK
			PL_CLK is 100MHz in current configuration
TRIP_CLEAR	W	1	trip clear. assert->deassert LSB to clear trip
PWM_STATUS	W	8	Bit[3:0] state of PWM
			sIDLE=4'b0001
			sNORMAL=4'b0010
			sTRIP = 4'b0100
			Bit[6:4] Trip status
			NO_TRIP = 3'b000
			EXT_TRIP = 3'b001
			SINC0_TRIP = 3'b010
			SINC1_TRIP = 3'b100
			Bit[7] actual level of external trip pin. Active low
TON_A	W	16	Sets the turn-on time for Phase A high-side gate signal
			Must be smaller than MASTER_CNT_MAX
			Must be smaller than TOFF_A
TOFF_A	W	16	Sets the turn-off time for the Phase A high-side gate signal
			Must be smaller than MASTER_CNT_MAX
			Must be smaller than TON_A
TON_B	W	16	Sets the turn-on time for Phase B high-side gate signal
			Must be smaller than MASTER_CNT_MAX
			Must be smaller than TOFF_A
TOFF_B	W	16	Sets the turn-off time for the Phase B high-side gate signal
			Must be smaller than MASTER_CNT_MAX
			Must be smaller than TON_B
TON_C	W	16	Sets the turn-on time for Phase C high-side gate signal
			Must be smaller than MASTER_CNT_MAX
			Must be smaller than TOFF_C
TOFF_C	W	16	Sets the turn-off time for the Phase C high-side gate signal
			Must be smaller than MASTER_CNT_MAX
			Must be smaller than TON_C
REG_GLOBAL_IRQ_EN	W	1	Global enable of IRQ from SINC filter​
			To disable set REG_GLOBAL_IRQ_EN[0]=0​
			To enable set REG_GLOBAL_IRQ_EN[0]=1​
REG_IRQ_EN	W	2	Enable of individual IRQs from PWM Block
			REG_IRQ_EN [0] control PWM_SYNC_IRQ
			REG_IRQ_EN [1] control PWM_TRIP_IRQ​
			To disable set REG_IRQ_EN [x]=0
			To enable set REG_IRQ_EN[x]=1
REG_IRQ_ACK	W	1	IRQ acknowledge
			REG_IRQ_ACK[0]=1 indicates acknowledge of PWM_SYNC_IRQ
			REG_IRQ_ACK[1]=1 indicates acknowledge of PWM_TRIP_IRQ​
REG_IRQ_PEN	R	2	IRQ pending
			REG_IRQ_PEN[0]=1 indicates PWM_SYNC_IRQ pending
			REG_IRQ_PEN[1]=1 indicates PWM_TRIP_IRQ​ pending​
REG_IRQ_STATUS	R	2	Sticky IRQ status
			REG_IRQ_STATUS[0]=1 indicates PWM_SYNC_IRQ has been asserted​
			REG_IRQ_STATUS[1]=1 indicates PWM_TRIP_IRQ has been asserted

PWM Timing

With the PWM Scheduler the user defines a turn_on event and a turn_off event. There are no assumptions made on modulation.
The scheduler runs from [0...MASTER_CNT_MAX]. For symmetric PWM, t-off = TM-t-on

Dead Time

The PWM module inserts dead time under all circumstances​

• Normal modulation​
• At modulation index ~0/~max​
• Transition to/from constantly on/off​
  • After having entered full on/off we do NOT want to insert dead time​
• When external sync comes earlier than expected​
• When external sync comes later than expected

With external sync it is not known how long the PWM period is going to be, which makes it harder to schedule dead time.​ At high modulation, dead time can extend into the follow-on PWM period -> dead time cannot be scheduled off the main timer​

Calculating Duty Cycles

Typically a motor-control algorithm outputs duty-cycles (D) for each phase. Applied phase voltage increases proportionally with D. D=0.5 means zero voltage, D<0.5 means negative voltage and D>0.5 is positive voltage.

The implemented PWM timer takes turn-on and turn-off time as input. That means the application must translate duty-cycles into turn-on/turn-off times. With symmetrical PWM and 16-bit fixed-point representation of the duty-cycle, the calculation per phase looks like this:

    temp = ((uint32_t)duty * PWM_CNT_MAX) >> 17;  

    TON = MASTER_CNT_MAX>>1 - temp;  
    TOFF = MASTER_CNT_MAX>>1 + temp;  

High Modulation Index

At high modulation (TON=~0 and TOFF=~ MASTER_CNT_MAX) pulses may be narrow or skipped.

With dead-time insertion, the PWM periods can start to overlap -> turn off for period 1 happens in period 2. With a narrow pulse, dead time is inserted twice. And with a skipped pulse dead time is inserted once (unless full on, i.e. clamp)

No matter what, dead time is always inserted, even if it overlaps with the following period.

Low Modulation Index

At low modulation (TON =~ TOFF) pulses may be skipped. With a narrow pulse, dead time is inserted twice. With a skipped pulse, dead time is inserted once (unless full off, i.e. clamp). Dead time is always inserted.

---

Back to FPGA Architecture home