Servo Drive Platform FPGA Architecture QEP

Encoder IF for the FPGA

Features of the QEP (Quadrature Encoder Pulse)

The QEP IP in the Intel Cyclone V FPGA has the following features:

• Quadrature encoder for 2-bit grey code​
• Position capture by index pulse​
• Minimum pulse filter on all input signals​
• Clock-domain synchronization on all input signals​
• Synchronization to PWM possible​
• Position measurement​
  • With and without synchronization to external trigger​
• N-by-1 speed measurement​
  • With and without synchronization to external trigger​
• N-by-N speed measurement​
  • With and without synchronization to external trigger​
• Configurable clockwise/counter-clockwise rotation​
• Configurable position roll-over​
• Position direction detection​

QEP Implementation

Incremental encoders continue to be a very popular position sensor​. The purpose of this block is to decode a 2-bit grey code from an incremental encoder into a rotor position and speed measurement​. The block also acts as an interface for 3 hall elements (absolute position).

QEP IP Block Diagram

Here is a functional block diagram of the QEP IP implementation in the Intel FPGA:

QEP IP I/O

Signal	Direction	I/O Standard	Description
A	input	3.3V CMOS	A line from encoder. Route to external pin
B	input	3.3V CMOS	B line from encoder. Route to external pin
Z	input	3.3V CMOS	Index line from encoder. Route to external pin
HALL[2:0]	input	3.3V CMOS	Hall signal input. 3-bit absolute position
sync_strobe[2:0]	input	n/a	Synchronization-pulse input. Typically driven by PWM sync

Registers

Register	R/W	Bits	Description
QEP_RESET	W	1	QEP module reset. Assert->deassert LSB of register before using module
QEP_ENABLE	W	1	QEP module enable. LSB of register must be asserted before using module
QEP_CONFIG	W	7	Bit [0] A line active level. 0 = active-high A pulse. 1 = active-low A pulse
			Bit [1] B line active level. 0 = active-high B pulse. 1 = active-low B pulse
			Bit [2] Z line active level. 0 = active-high index pulse. 1 = active low index pulse.
			Bit [3] Count direction. 0 = Positive count direction. 1 = Negative count direction
			Bit [5:4] index mode. 01 = Capture on rising edge. 10 = Capture on falling edge
			Bit [6] Sync enable. 0 = Disable sync to external pulse. 1= Enable sync to external pulse
QEP_MPW_CNT	W	32	Sets the minimum pulse width to be ignored
			t_mpw=QEP_MPW_CNT/PL_CLK PL_CLK is 100Mhz in current configuration
QEP_CNT_WRAP	W	32	Counter wrap-around value
QEP_CNT	R	32	Current counter value.​ Updated at every A/B count event
QEP_CNT_IDX_LATCH	R	32	Counter value captured at index pulse.​ Updated at active edge of index pulse
QEP_CNT_STROBE_LATCH	R	32	Counter value captured at external sync pulse
			Updated each time external sync pulse is asserted
QEP_HALL	R	3	Filtered hall states: [Hall 2, Hall 1, Hall 0]
QEP_M	W	32	Number of A/B count events between capture of N/M speed measurement
			For best results, set M to 2^i with i=1,2,3…
QEP_N_BY_M	R	32	Number (N) of PL_CLKs between M A/B count events​
			N is number of PL_CLKs since last capture
			Low-noise speed measurement, especially effective at higher speed
QEP_N_BY_1	R	32	Number (N) of PL_CLKs between two A/B count events​
			N is number of PL_CLKs since last capture (see note 1)
			​

note 1

With poor encoders, this speed measurement tends to be noisy but signal can be helpful at low speed as it is updated more often than QEP_N_BY_M (M times more often).

Back to FPGA Architecture home