ADRV9371 Platform modify the existing hdl project

Follow these steps to...

• examine the repository structure
• examine the build process
• examine the files required for a project build
• copy an existing base_design/board design
• modify it to create a new one
• execute the build

1 - Examine the repository file structure

2 - Examine the build process

A typical build command would be executed from a shell from the hdl directory. Generically, it would look like this:

$ make <board_design>.<base_design>  

A specific example would be

 $ make ad9371x.a10soc  

A makefile representing the specific base design for that particular board design is located in the **hdl/projects/<board_design>/<base_design> directory

This makefile includes a generic project-altera.mk which will perform builds for all IntelPSG base board projects.

3 - Examine files required for project build

The following files must be present for a successful build flow in these specific folders

• project/<board_design>/base_design>
  • system_top.v -top level verilog hdl file
  • system_qsys -top level qsys tcl file. Qsys system is subdivided into three main sections
  • projects/common/<base_design>/<base_design>_system_qsys.tcl -common system peripherals such as hps component, hps ddr4, gpio, spi master, gpio etc
  • projects/common/<base_design>/<base_design>_plddr4_dacfifo_qsys.tcl -fpga ddr4 fifo user to buffer high speed data
  • projects/<board_design>/common/<board_design>_qsys.tcl -converter and jesd204b qsys system common to a board_design for multiple base_designs
  • system_project.tcl -quartus tcl build script including converter and jesd204b transceiver and converter specific assignments
  • system_constr.sdc -timequest constraints for the quartus project
  • Makefile - makefile for a base_design specific to a board_design
• projects/<board_design>/common
  • <board_design>_qsys.tcl - converter and jesd204b qsys system common to a board_design for multiple base_designs
• projects/common/<base_design>
  • <base_design>_system_qsys.tcl - common system peripherals such as hps component, hps ddr4, gpio, spi master, gpio etc
  • <base_design>_system_assign.tcl - quartus assignments for common system peripherals such as hps component, hps ddr4, gpio, spi master, gpio etc
  • <base_design>_plddr4_dacfifo_qsys.tcl - fpga ddr4 fifo used to buffer high speed data
  • <base_design>_plddr4_dacfifo_assign.tcl - quartus assignments for fpga ddr4 fifo used to buffer high speed data
• library/axi_<converter_component/s>
  • In this case the ip exists in the component folder library/axi_ad9371. It includes an axi_ad9371_hw.tcl qsys component definition file. This is obviously a complex component.
• projects/scripts
  • adi_project_alt.tcl - tool revision and base_board specific build information

4 - Copy an existing base_design for an existing board_design project to a new folder and rename it to create a new one

• Select an appropriate name for the new base_design. Based on the Critical Link™ product naming convention an example might be mitysom_a10s

• In this instance the final design is based on arria 10 soc technology. Copy

        $ cp projects/ad9371x/a10soc projects/ad9371x/mitysom_a10s  
  

• Then

        $ cp project/common/a10s0c project/common/mitysom_a10s  
  

• Change all file names from a10soc_ to mitysom_a10s_

5 - Modify the copied design files and folders to complete the ad9371_mitysom_a10s project

• edit project/scripts/adi_project_alt.tcl add an entry for mitysom_a10s
• edit project/common/mitysom_a10s_system_qsys.tcl, and project/common/mitysom_a10s_system_assign.tcl
  • modify the appropriate HPS components to match the som, io_dedicated, io_shared, and ddr controller settings
  • modify the associated Quartus™ pin placement, io_standard, etc assignments
• edit project/common/mitysom_a10s_system_plddr4_dacfifo_qsys.tcl, and project/common/mitysom_a10s_pldrdr4_assign.tcl
  • modify appropriate FPGA ddr controller settings
  • modify associated Quartus™ pin placement, io_standard, etc assignments
• edit project/ad9371x/mitysom_a10s files
• edit the Makefile. change all a10soc references to mitysom_a10s
• edit the system_qsys.tcl change all a10soc references to mitysom_a10s
• edit the system_project.tcl change all a10soc references to mitysom_a10s
  • modify pin location assignments, etc
• edit the system_top.v add or remove signals when porting from Intel PSG A10™ SoC development kit to the MitySOM™ development kit
  • edit the system_constr.sdc. modify clock definitions where necessary

6 - Execute the build

• Open a Nios II™ command shell for Quartus Prime™ 18.0 from your install area:

The shell will look something like this:

• cd to the hdl directory

      $ cd <path to ADRV9371 project location on your machine>/hdl  
  

• execute the build

    $ make adrv9371x.mitysome_a10s  
  

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