jesd204b interface framework

JESD204B Interface Framework

The JESD204, JESD204A and the JESD204B data converter serial interface standard was created through the JEDEC committee to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs (field-programmable gate arrays). Fewer interconnects simplifies layout and allows smaller form factor realization without impacting overall system performance. These attributes are important to address the system size and cost constraints of a range of high speed ADC applications, including wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA) transceiver architectures, software-defined radios, portable instrumentation, medical ultrasound equipment, and Mil/Aero applications such as radar and secure communications. Analog Devices is an original participating member of the JEDEC JESD204 standards committee and we have concurrently developed compliant data converter technology and tools, and a comprehensive product roadmap to fully enable our customers to take advantage of this significant interfacing breakthrough.

Analog Devices supplies a full-stack supporting JESD204B which provides a fully integrated system level experience. This solution includes

• Reference hardware platforms for rapid-prototyping
• FPGA HDL for interfacing JESD204B ADCs, DACs, and RF Transceivers
• Software to configure the converter devices and FPGA HDL peripherals

How to Obtain a License

When customers and partners download software from github, or e-mail downloaded software to someone, they are obligated to comply to the terms and conditions of the Software License Agreement. The core is released under two different licenses. You may choose either:

• Commercial licenses may be purchased from Analog Devices, Inc. or any authorized distributor by ordering AD-IP-JESD204. This will allow you to use the core in a closed system.
• GPL 2, this allows you to use the core for any purpose, but you must release anything else that links to the JESD204 core (this would normally be your algorithmic IP). You do not need to sign anything or purchase anything to use the JESD204 core under the GPL license.

There is only one core, the only difference is the license and support. If you have a question about the license: you can email [email protected].

FPGA HDL Support

The JESD204B standard defines multiple layers, each layer being responsible for a particular function. The Analog Devices JESD204B HDL solution follows the standard here and defines 4 layers. Physical layer, link layer, transport layer and application layer. For the first three layers Analog Devices provides standard components that can be linked up to provide a full JESD204B protocol processing chain.

Depending on the FPGA and converter combinations that are being interfaced different components can be chosen for the physical and transport layer. The FPGA defines which physical layer component should be used and the interfaced converter defines which transport layer component should be used.

The link layer component is selected based on the direction of the JESD204B link.

The application layer is user defined and can be used to implement application specific signal processing.

Physical Layer

Physical layer peripherals are responsible for interfacing and configuring the high-speed serial transceivers.

• AXI_ADXCVR: JESD204B Gigabit Transceiver Register Configuration Peripheral

Link Layer

Link layer peripherals are responsible for JESD204B protocol handling, including scrambling/descrambling, lane alignment, character replacement and alignment monitoring.

• JESD204B Transmit Peripheral: JESD204B Link Layer Transmit Peripheral
• JESD204B Receive Peripheral: JESD204B Link Layer Receive Peripheral

Transport Layer

Transport layer peripherals are responsible for converter specific data framing and de-framing.

• ADC JESD204B Transport Peripheral : JESD204B Transport Layer Receive Peripheral
• DAC JESD204B Transport Peripheral : JESD204B Transport Layer Transmit Peripheral

Interfaces

Interfaces are a well-defined collection of wires that are used to communicate between components. The following interfaces are used to connect components of the HDL JESD204B processing stack.

Software Support

Linux

• JESD204B Transmit Linux Driver: Linux driver for the JESD204B transmit core.
• JESD204B Receive Linux Driver: Linux driver for the JESD204B receive core.

No-OS

Tutorial

• Introduction
• System Architecture
• DAQ2 HDL Altera
• Linux

Example Projects

• AD-FMCJESDADC1-EBZ HDL Reference Design
  • Intel A10GX
  • Intel A10SOC
• AD-FMCDAQ2-EBZ HDL Reference Design
  • Intel A10GX
  • Intel A10SOC
• ADRV9371 HDL Reference Design
  • Intel A10GX
  • Intel A10SOC
  • Critical Link A10SOC

Additional Information

• JESD204B Glossary

Technical Articles

• JESD204B Survival Guide
• Synchronizing Sample Clocks of a Data Converter Array

JESD204B Rapid Prototyping Platforms

• Critical Link® MitySOM®-A10S Development Kit
• ADRV971 Platform Architecture
• iWave Arria 10 SoC/FPGA FMC Development Platform
• AD-FMCDAQ2 Platform Architecture
• EVAL-ADRV9371 (User Guide)
• EVAL-ADRV9008
• AD-FMCJESDADC1-EBZ
• AD-FMCADC2-EBZ
• EVAL-AD-FMCADC3-EBZ
• EVAL-AD-FMCADC4-EBZ
• AD-FMCDAQ2-EBZ

JESD204B Analog-to-Digital Converters

• AD6673: 80 MHz Bandwidth, Dual IF Receiver
• AD6674: 385 MHz BW IF Diversity Receiver
• AD6676: Wideband IF Receiver Subsystem
• AD6677: 80 MHz Bandwidth, IF Receiver
• AD6684: 135 MHz Quad IF Receiver
• AD6688: RF Diversity and 1.2GHz BW Observation Receiver
• AD9208: 14-Bit, 3GSPS, JESD204B, Dual Analog-to-Digital Converter
• AD9234: 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter
• AD9250: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter
• AD9625: 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter
• AD9656: Quad, 16-Bit, 125 MSPS JESD204B 1.8 V Analog-to-Digital Converter
• AD9680: 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter
• AD9683: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter
• AD9690: 14-Bit, 500 MSPS / 1 GSPS JESD204B, Analog-to-Digital Converter
• AD9691: 14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter
• AD9694: 14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter

JESD204B Digital-to-Analog Converters

• AD9135: Dual, 11-Bit, high dynamic, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter
• AD9136: Dual, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter
• AD9144: Quad, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter
• AD9152: Dual, 16-Bit, 2.25 GSPS, TxDAC+ Digital-to-Analog Converter
• AD9154: Quad, 16-Bit, 2.4 GSPS, TxDAC+® Digital-to-Analog Converter
• AD9161: 11-Bit, 12 GSPS, RF Digital-to-Analog Converter
• AD9162: 16-Bit, 12 GSPS, RF Digital-to-Analog Converter
• AD9163: 16-Bit, 12 GSPS, RF DAC and Digital Upconverter
• AD9164: 16-Bit, 12 GSPS, RF DAC and Direct Digital Synthesizer
• AD9172: Dual, 16-Bit, 12 GSPS RF DAC with Channelizers

JESD204B RF Transceivers

• AD9371: SDR Integrated, Dual RF Transceiver with Observation Path
• ADRV9009: SDR Integrated, Dual RF Transceiver with Observation Path

JESD204B Clocking Solutions

• AD9528: JESD204B Clock Generator with 14 LVDS/HSTL Outputs
• HMC7043: High Performance, 3.2 GHz, 14-Output Fanout Buffer
• HMC7044: High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B

Next- IIO Oscilloscope

Return to Table of Contents

Return to Arrow High-Speed Converter Platforms

Information from this site was obtained from