adc transport peripheral
The ADC JESD204B Transport Peripheral implements the transport level handling of a JESD204B transmitter device. It is compatible with a wide range of Analog Devices high-speed analog-to-digital converters.
The core handles the JESD204B de-framing of the payload data.
The peripheral can be configured at runtime through a AXI4-Lite memory mapped register map.
- ADI high-speed ADC compatible JESD204B data de-framing
- Test-pattern checker
- Per-channel data formating (sign-extension, two's complement to offset binary)
- Runtime re-configurability through memory-mapped register interface (AXI4-Lite)
[up_adc_common.v]
[axi_ad9371_rx_channel.v]
[axi_ad9371_rx.v]
| Name | Description | Default |
|---|---|---|
| ID | Instance identification number. | 0 |
| ADC_DATAPATH_DISABLE | ADC data path disabled | 0 |
| Name | Type | Description |
|---|---|---|
| s_axi_aclk | Clock | All S_AXI signals are synchronous to this clock. |
| s_axi_aresetn | Synchronous active low reset | Resets the internal state of the peripheral. |
| S_AXI | AXI4-Lite bus slave | Memory mapped AXI-lite bus that provides access to modules register map. |
| Link layer interface | ||
| link_clk | Clock | Device clock for the JESD204B interface. Must be line clock / 40 for correct operation. |
| LINK_DATA | AXI4-Streaming interface slave | JESD204 link data interface. |
| Application layer interface | ||
| adc_clk | Input | ADC Clock. |
| adc_data | Input | Raw application layer data, every channel concatenated. |
| adc_dovf | Input | Application layer overflow. |
| adc_dunf | Input | Application layer underflow. |
| adc_rst | Output | Reset to the ADC |
| adc_enable_i0 | Output | ADC I-Channel 0 enable indicator. |
| adc_valid_i0 | Output | ADC I-Channel 0 data valid indicator (Always '1'). |
| adc_data_i0 | Output | ADC I-Channel 0 data. |
| adc_enable_q0 | Output | ADC Q-Channel 0 enable indicator. |
| adc_valid_q0 | Output | ADC Q-Channel 0 data valid indicator (Always '1'). |
| adc_data_q0 | Output | ADC Q-Channel 0 data. |
| adc_enable_i1 | Output | ADC I-Channel 1 enable indicator. |
| adc_valid_i1 | Output | ADC I-Channel 1 data valid indicator (Always '1'). |
| adc_data_i1 | Output | ADC I-Channel 1 data. |
| adc_enable_q1 | Output | ADC Q-Channel 1 enable indicator. |
| adc_valid_q1 | Output | ADC Q-Channel 1 data valid indicator (Always '1'). |
| adc_data_q1 | Output | ADC Q-Channel 1 data. |
The S_AXI interface is synchronous to the s_axi_aclk clock. All other signals and interfaces are synchronous to the device_clk clock.
The register map of the core contains instances of several generic register maps like ADC common, ADC channel, DAC common, DAC channel etc. The following table presents the base addresses of each instance, after that can be found the detailed description of each generic register map. The absolute address of a register should be calculated by adding the instance base address to the registers relative address.
| Address | Name | Description | |||
|---|---|---|---|---|---|
| DWORD | BYTE | ||||
| 0x0000 | 0x0000 | BASE | See the Base (common to all cores) table for more detail | ||
| 0x0100 | 0x0400 | ADC CHANNEL 0 | See the ADC Channel table for more detail | ||
| 0x0110 | 0x0440 | ADC CHANNEL 1 | See the ADC Channel table for more detail | ||
| 0x0120 | 0x0480 | ADC CHANNEL 2 | See the ADC Channel table for more detail | ||
| 0x0130 | 0x04C0 | ADC CHANNEL 3 | See the ADC Channel table for more detail |
| Address | Bits | Name | Type | Default | Description |
|---|---|---|---|---|---|
| DWORD BYTE | |||||
| 0x0000 | 0x0000 | REG_VERSION | Version and Scratch Registers | ||
| [31:0] | VERSION[31:0] | RO | 0x00000000 | Version number. Unique to all cores. | |
| 0x0001 | 0x0004 | REG_ID | Version and Scratch Registers | ||
| [31:0] | ID[31:0] | RO | 0x00000000 | Instance identifier number. | |
| 0x0002 | 0x0008 | REG_SCRATCH | Version and Scratch Registers | ||
| [31:0] | SCRATCH[31:0] | RW | 0x00000000 | Scratch register. | |
| 0x0003 | 0x000c | REG_CONFIG | Version and Scratch Registers | ||
| [0] | IQCORRECTION_DISABLE | RO | 0x0 | If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance) | |
| [1] | DCFILTER_DISABLE | RO | 0x0 | If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance) | |
| [2] | DATAFORMAT_DISABLE | RO | 0x0 | If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance) | |
| [3] | USERPORTS_DISABLE | RO | 0x0 | If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance) | |
| [4] | MODE_1R1T | RO | 0x0 | If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet) | |
| [5] | DELAY_CONTROL_DISABLE | RO | 0x0 | If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance) | |
| [6] | DDS_DISABLE | RO | 0x0 | If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance) | |
| [7] | CMOS_OR_LVDS_N | RO | 0x0 | CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance) | |
| [8] | PPS_RECEIVER_ENABLE | RO | 0x0 | If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance) | |
| [9] | SCALECORRECTION_ONLY | RO | 0x0 | If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance) | |
| 0x0004 | 0x0010 | REG_PPS_IRQ_MASK | PPS Interrupt mask | ||
| [0] | PPS_IRQ_MASK | RW | 0x1 | Mask bit for the 1PPS receiver interrupt | |
| 0x0010 | 0x0040 | REG_RSTN | ADC Interface Control & Status | ||
| [2] | CE_N | RW | 0x0 | Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables | |
| [1] | MMCM_RSTN | RW | 0x0 | MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. | |
| [0] | RSTN | RW | 0x0 | Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. | |
| 0x0011 | 0x0044 | REG_CNTRL | ADC Interface Control & Status | ||
| [4] | SREF_SYNC | RW | 0x0 | Reference synchronization between multiple ADCs | |
| [3] | SYNC | RW | 0x0 | Initialize synchronization between multiple ADCs | |
| [2] | R1_MODE | RW | 0x0 | Select number of RF channels 1 (0x1) or 2 (0x0). | |
| [1] | DDR_EDGESEL | RW | 0x0 | Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers. | |
| [0] | PIN_MODE | RW | 0x0 | Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge. | |
| 0x0015 | 0x0054 | REG_CLK_FREQ | ADC Interface Control & Status | ||
| [31:0] | CLK_FREQ[31:0] | RO | 0x0000 | Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock. | |
| 0x0016 | 0x0058 | REG_CLK_RATIO | ADC Interface Control & Status | ||
| [31:0] | CLK_RATIO[31:0] | RO | 0x0000 | Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr). | |
| 0x0017 | 0x005c | REG_STATUS | ADC Interface Control & Status | ||
| [3] | PN_ERR | RO | 0x0 | If set, indicates pn error in one or more channels. | |
| [2] | PN_OOS | RO | 0x0 | If set, indicates pn oos in one or more channels. | |
| [1] | OVER_RANGE | RO | 0x0 | If set, indicates over range in one or more channels. | |
| [0] | STATUS | RO | 0x0 | Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores. | |
| 0x001A | 0x0068 | REG_SYNC_STATUS | ADC Synchronization Status register | ||
| [0] | ADC_SYNC | RO | 0x0 | ADC synchronization status. Will be set to 1 after the synchronization has been successfully completed | |
| 0x001C | 0x0070 | REG_DRP_CNTRL | ADC Interface Control & Status | ||
| [28] | DRP_RWN | RW | 0x0 | DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). | |
| [27:16] | DRP_ADDRESS[11:0] | RW | 0x00 | DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). | |
| [15:0] | RESERVED[15:0] | RO | 0x0000 | Reserved for backward compatibility. | |
| 0x001D | 0x0074 | REG_DRP_STATUS | ADC Interface Control & Status | ||
| [17] | DRP_LOCKED | RO | 0x0 | If set indicates that the DRP has been locked. | |
| [16] | DRP_STATUS | RO | 0x0 | If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). | |
| [15:0] | RESERVED[15:0] | RO | 0x00 | Reserved for backward compatibility. | |
| 0x001E | 0x0078 | REG_DRP_WDATA | ADC DRP Write Data | ||
| [31:0] | DRP_WDATA[31:0] | RW | 0x00 | DRP write data. NOT-APPLICABLE if DRP_DISABLE is set (0x1). | |
| 0x001F | 0x007c | REG_DRP_RDATA | ADC DRP Read Data | ||
| [15:0] | DRP_RDATA[15:0] | RO | 0x00 | DRP read data (does not include GTX lanes). | |
| 0x0022 | 0x0088 | REG_UI_STATUS | User Interface Status | ||
| [2] | UI_OVF | RW1C | 0x0 | User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. | |
| [1] | UI_UNF | RW1C | 0x0 | User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. | |
| [0] | UI_RESERVED | RW1C | 0x0 | Reserved for backward compatibility. | |
| 0x0023 | 0x008c | CONSTANT | Fixed Value | ||
| [31:0] | CONSTANT[31:0] | RW | 0x00000008 | Fixed to 0x008. | |
| 0x0028 | 0x00a0 | REG_USR_CNTRL_1 | ADC Interface Control & Status | ||
| [7:0] | USR_CHANMAX[7:0] | RW | 0x00 | This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| 0x0029 | 0x00a4 | REG_ADC_START_CODE | ADC Synchronization start word | ||
| [31:0] | ADC_START_CODE[31:0] | RW | 0x00000000 | This sets the startcode that is used by the ADCs for synchronization NOT-APPLICABLE if START_CODE_DISABLE is set (0x1). | |
| 0x002E | 0x00b8 | REG_ADC_GPIO_IN | ADC GPIO inputs | ||
| [31:0] | ADC_GPIO_IN[31:0] | RO | 0x00000000 | This reads auxiliary GPI pins of the ADC core | |
| 0x002F | 0x00bc | REG_ADC_GPIO_OUT | ADC GPIO outputs | ||
| [31:0] | ADC_GPIO_OUT[31:0] | RW | 0x00000000 | This controls auxiliary GPO pins of the ADC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1). | |
| 0x0030 | 0x00c0 | REG_PPS_COUNTER | PPS Counter register | ||
| [31:0] | PPS_COUNTER[31:0] | RO | 0x00000000 | Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse. | |
| 0x0031 | 0x00c4 | REG_PPS_STATUS | PPS Status register | ||
| [0] | PPS_STATUS | RO | 0x0 | If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it's not active. | |
| 0x0040 | 0x0100 | UP_TIMER | Timer Register | ||
| [31:0] | UP_TIMER[31:0] | RO | 0x00000000 | Counts down to 0 from a value written in the register. |
| Address | Bits | Name | Type | Default | Description |
|---|---|---|---|---|---|
| DWORD | BYTE | ||||
| 0x0000 | 0x0000 | REG_CHAN_CNTRL | ADC Interface Control & Status | ||
| [11] | ADC_LB_ENB | RW | 0x0 | If set, forces ADC_DATA_SEL to 1, enabling data loopback | |
| [10] | ADC_PN_SEL | RW | 0x0 | If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) If both ADC_PN_TYPE and ADC_PN_SEL are set, they are ignored | |
| [9] | IQCOR_ENB | RW | 0x0 | if set, enables IQ correction or scale correction. NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). | |
| [8] | DCFILT_ENB | RW | 0x0 | if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). | |
| [6] | FORMAT_SIGNEXT | RW | 0x0 | if set, enables sign extension (applicable only in 2's complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1). | |
| [5] | FORMAT_TYPE | RW | 0x0 | Select offset binary (0x1) or 2's complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1). | |
| [4] | FORMAT_ENABLE | RW | 0x0 | Enable data format conversion (see register bits above). NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1). | |
| [3] | RESERVED | RO | 0x0 | Reserved for backward compatibility. | |
| [2] | RESERVED | RO | 0x0 | Reserved for backward compatibility. | |
| [1] | ADC_PN_TYPE | RW | 0x0 | If set, forces ADC_PN_SEL to 0x1, modified pn23 If both ADC_PN_TYPE and ADC_PN_SEL are set, they are ignored | |
| [0] | ENABLE | RW | 0x0 | If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected. | |
| 0x0001 | 0x0004 | REG_CHAN_STATUS | ADC Interface Control & Status | ||
| [2] | PN_ERR | RW1C | 0x0 | PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared. | |
| [1] | PN_OOS | RW1C | 0x0 | PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern. | |
| [0] | OVER_RANGE | RW1C | 0x0 | If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards. | |
| 0x0004 | 0x0010 | REG_CHAN_CNTRL_1 | ADC Interface Control & Status | ||
| [31:16] | DCFILT_OFFSET[15:0] | RW | 0x0000 | DC removal (if equipped) offset. This is a 2's complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). | |
| [15:0] | DCFILT_COEFF[15:0] | RW | 0x0000 | DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). | |
| 0x0005 | 0x0014 | REG_CHAN_CNTRL_2 | ADC Interface Control & Status | ||
| [31:16] | IQCOR_COEFF_1[15:0] | RW | 0x0000 | IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel with the format 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). | |
| [15:0] | IQCOR_COEFF_2[15:0] | RW | 0x0000 | IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). | |
| 0x0006 | 0x0018 | REG_CHAN_CNTRL_3 | ADC Interface Control & Status | ||
| [19:16] | ADC_PN_SEL[3:0] | RW | 0x0 | Selects the PN monitor sequence type (available only if ADC supports it). 0x0: pn9a (device specific, modified pn9) 0x1: pn23a (device specific, modified pn23) 0x4: pn7 (standard O.150) 0x5: pn15 (standard O.150) 0x6: pn23 (standard O.150) 0x7: pn31 (standard O.150) 0x9: pnX (device specific, e.g. ad9361) | |
| [3:0] | ADC_DATA_SEL[3:0] | RW | 0x0 | Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC) | |
| 0x0008 | 0x0020 | REG_CHAN_USR_CNTRL_1 | ADC Interface Control & Status | ||
| [25] | USR_DATATYPE_BE | RO | 0x0 | The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| [24] | USR_DATATYPE_SIGNED | RO | 0x0 | The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| [23:16] | USR_DATATYPE_SHIFT[7:0] | RO | 0x00 | The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| [15:8] | USR_DATATYPE_TOTAL_BITS[7:0] | RO | 0x00 | The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| [7:0] | USR_DATATYPE_BITS[7:0] | RO | 0x00 | The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| 0x0009 | 0x0024 | REG_CHAN_USR_CNTRL_2 | __ADC Interface Control & Statusv | ||
| [31:16] | USR_DECIMATION_M[15:0] | RW | 0x0000 | This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| [15:0] | USR_DECIMATION_N[15:0] | RW | 0x0000 | This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| 0x0010 | 0x0040 | REG_* | Channel 1, similar to register 0x100 to 0x10f. | ||
| 0x0020 | 0x0080 | REG_* | Channel 2, similar to register 0x100 to 0x10f. | ||
| 0x00F0 | 0x03c0 | REG_* | __Channel 15, similar to register 0x100 to 0x10f.v |
The peripheral features a register map configuration interface that can be accessed through the AXI4-Lite ''S_AXI'' port. The register map can be used to configure the peripherals operational parameters, query the current status of the device and query the features supported by the device.
The link layer interface description can be found in the User Data Interface section of the JESD204B Link Receive Peripheral IP.
The application layer is connected to the deframer block output. The deframer module creates sample data from the lane mapped and formatted JESD204 link data based on the specified deframer configuration.
The data in the application layer interface adc_data has the following layout:
MSB LSB
[ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ]
Where MjSi refers to the i-th sample of the j-th converter. With m being the number of converters and n the number of samples per converter per beat.
The core asserts the enable signal for each channel that is enabled by the software.
The REG_STATUS (0x054) register CLK_FREQ field allows to determine the clock rate of the device clock (link_clk) relative to the AXI interface clock (s_axi_aclk). This can be used to verify that the device clock is running at the expected rate.
The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 indicates that the link clock is currently not active.
The component is configured by the REG_CHAN_CNTRL register FORMAT_SIGNEXT,FORMAT_TYPE,FORMAT_ENABLE fields. The block introduces one clock cycle latency.
The block can monitor and compare the incoming deframed raw data against PN9 or PN23 patterns selected by the ADC_PN_SEL field of REG_CHAN_CNTRL_3 register.
| ADC_PN_SEL | PN |
|---|---|
| 0 | PN9 |
| others | PN23 |
For each channel mismatches are reported in PN_ERR and PN_OOS fields of the REG_CHAN_STATUS register.
To ensure correct operation it is highly recommended to use the Analog Devices provided JESD204B software packages for interfacing the peripheral. Analog Devices is not able to provide support in case issues arise from using custom low-level software for interfacing the peripheral.
Reduced number of octets-per-frame (F) settings. The following values are supported by the peripheral: 1, 2, 4
- AD6673
- AD6674
- AD6676
- AD6677
- AD6684
- AD6688
- AD9208
- AD9234
- AD9250
- AD9625
- AD9656
- AD9680
- AD9683
- AD9690
- AD9691
- AD9694
Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the EngineerZone.
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