dac transport peripheral
The DAC JESD204B Transport Peripheral (AD-IP-JESD204-TRANSPORT-DAC) implements the transport level handling of a JESD204B transmitter device. It is compatible with a wide range of Analog Devices high-speed digital-to-analog converters.
The core handles the JESD204B framing of the user-provided payload data. In addition it is capable of generating standard and user-defined test-pattern data for interface verification. It also features a per-channel dual-tone DDS that can be used to dynamically generate test-tones.
The peripheral can be configured at runtime through a AXI4-Lite memory mapped register map.
- ADI high-speed DAC compatible JESD204B data framing
- Test-pattern generator for interface verification
- Per-channel dual-tone DDS (optional)
- Runtime re-configurability through memory-mapped register interface (AXI4-Lite)
| Name | Description | Default |
|---|---|---|
| ID | Instance identification number. | 0 |
| NUM_LANES | Number of lanes supported by the peripheral. Equivalent to JESD204 L parameter. |
4 |
| NUM_CHANNELS | Number of converters supported by the peripheral. Equivalent to JESD204 M parameter. |
2 |
| SAMPLES_PER_FRAME | Number of samples per frame. Equivalent to JESD204 S parameter. |
1 |
| CONVERTER_RESOLUTION | Resolution of the converter. Equivalent to JESD204 N parameter. |
16 |
| BITS_PER_SAMPLE | Number of bits per sample. Equivalent to JESD204 NP parameter. |
16 |
| OCTETS_PER_BEAT | Number of bytes per beat for each link. | 4 |
| DDS_TYPE | DDS Type. Set 1 for CORDIC or 2 for Polynomial | 1 |
| DDS_CORDIC_DW | CORDIC DDS Data Width | 16 |
| DDS_CORDIC_PHASE_DW | CORDIC DDS Phase Width | 16 |
| DATAPATH_DISABLE | Disable instantiation of DDS core. | 0 |
| Name | Type | Description |
|---|---|---|
| Configuration interface | ||
| s_axi_aclk | Clock | All S_AXI signals and irq are synchronous to this clock. |
| s_axi_aresetn | Synchronous active low reset | Resets the internal state of the peripheral. |
| S_AXI | AXI4-Lite bus slave | Memory mapped AXI-lite bus that provides access to modules register map. |
| Link layer interface | ||
| link_clk | Clock | Device clock for the JESD204B interface. Must be line clock / 40 for correct operation. |
| LINK_DATA | AXI4-Streaming interface | Framed transmit data towards link layer. |
| Application layer interface | ||
| enable | Output | Request signal for each channel. |
| dac_valid | Output | Qualifier signal for each channel. Always '1'. |
| dac_ddata | Input | Raw application layer data, every channel concatenated. |
| dac_dunf | Input | Application layer underflow. |
The register map of the core contains instances of several generic register maps like ADC common, ADC channel, DAC common, DAC channel etc. The following table presents the base addresses of each instance, after that can be found the detailed description of each generic register map. The absolute address of a register should be calculated by adding the instance base address to the registers relative address.
| Address | Name | Description | |
|---|---|---|---|
| DWORD | BYTE | ||
| 0x0000 | 0x0000 | BASE | See the Base (common to all cores) table for more detail |
| 0x0010 | 0x0040 | DAC COMMON | See the DAC Common table for more detail |
| 0x0080 | 0x0200 | DAC TPL | See the JESD TPL table for more detail |
| 0x0100 | 0x0400 | DAC CHANNELS | See the DAC Channel table for more detail |
The data is intended for the DAC can have multiple sources:
- DMA source Raw data can be accepted from a external block representing the Application layer.
- DDS source For each DAC channel a dual-tone can be generated by a DDS core.
- PRBS source For each DAC channel one of the following PN sequence can be selected: PN7, PN15, inverted PN7, inverted PN15
The application layer connects to the framer block when the DMA source is selected. The framer module takes sample data and maps it onto the format that the JESD204 link expects for the specified framer configuration.
The data in the application layer interface dac_ddata is expected to have the following layout:
MSB LSB
[ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ]
Where MjSi refers to the i-th sample of the j-th converter. With m being the number of converters and n the number of samples per converter per beat.
The core asserts the enable signal for each channel that is enabled by the software. The dac_ddata data bus must contain data for each channel regardless if the channels are enabled or not.
The link layer interface description can be found in the User Data Interface section of the JESD204B Link Transmit Peripheral IP.
The REG_STATUS (0x054) register CLK_FREQ field allows to determine the clock rate of the device clock (link_clk) relative to the AXI interface clock (s_axi_aclk). This can be used to verify that the device clock is running at the expected rate.
The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 indicates that the link clock is currently not active.
Reduced number of octets-per-frame (F) settings. The following values are supported by the peripheral: 1, 2, 4
To ensure correct operation it is highly recommended to use the Analog Devices provided JESD204B software packages for interfacing the peripheral. Analog Devices is not able to provide support in case issues arise from using custom low-level software for interfacing the peripheral.
Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the https://ez.analog.com/community/fpga.