dac transport peripheral
The DAC JESD204B Transport Peripheral (AD-IP-JESD204-TRANSPORT-DAC) implements the transport level handling of a JESD204B transmitter device. It is compatible with a wide range of Analog Devices high-speed digital-to-analog converters.
The core handles the JESD204B framing of the user-provided payload data. In addition it is capable of generating standard and user-defined test-pattern data for interface verification. It also features a per-channel dual-tone DDS that can be used to dynamically generate test-tones.
The peripheral can be configured at runtime through a AXI4-Lite memory mapped register map.
- ADI high-speed DAC compatible JESD204B data framing
- Test-pattern generator for interface verification
- Per-channel dual-tone DDS (optional)
- Runtime re-configurability through memory-mapped register interface (AXI4-Lite)
| Name | Description | Default |
|---|---|---|
| ID | Instance identification number. | 0 |
| NUM_LANES | Number of lanes supported by the peripheral. Equivalent to JESD204 L parameter. |
4 |
| NUM_CHANNELS | Number of converters supported by the peripheral. Equivalent to JESD204 M parameter. |
2 |
| SAMPLES_PER_FRAME | Number of samples per frame. Equivalent to JESD204 S parameter. |
1 |
| CONVERTER_RESOLUTION | Resolution of the converter. Equivalent to JESD204 N parameter. |
16 |
| BITS_PER_SAMPLE | Number of bits per sample. Equivalent to JESD204 NP parameter. |
16 |
| OCTETS_PER_BEAT | Number of bytes per beat for each link. | 4 |
| DDS_TYPE | DDS Type. Set 1 for CORDIC or 2 for Polynomial | 1 |
| DDS_CORDIC_DW | CORDIC DDS Data Width | 16 |
| DDS_CORDIC_PHASE_DW | CORDIC DDS Phase Width | 16 |
| DATAPATH_DISABLE | Disable instantiation of DDS core. | 0 |
| Name | Type | Description |
|---|---|---|
| Configuration interface | ||
| s_axi_aclk | Clock | All S_AXI signals and irq are synchronous to this clock. |
| s_axi_aresetn | Synchronous active low reset | Resets the internal state of the peripheral. |
| S_AXI | AXI4-Lite bus slave | Memory mapped AXI-lite bus that provides access to modules register map. |
| Link layer interface | ||
| link_clk | Clock | Device clock for the JESD204B interface. Must be line clock / 40 for correct operation. |
| LINK_DATA | AXI4-Streaming interface | Framed transmit data towards link layer. |
| Application layer interface | ||
| enable | Output | Request signal for each channel. |
| dac_valid | Output | Qualifier signal for each channel. Always '1'. |
| dac_ddata | Input | Raw application layer data, every channel concatenated. |
| dac_dunf | Input | Application layer underflow. |
The register map of the core contains instances of several generic register maps like ADC common, ADC channel, DAC common, DAC channel etc. The following table presents the base addresses of each instance, after that can be found the detailed description of each generic register map. The absolute address of a register should be calculated by adding the instance base address to the registers relative address.
| Address | Name | Description | |
|---|---|---|---|
| DWORD | BYTE | ||
| 0x0000 | 0x0000 | BASE | See the Base (common to all cores) table for more detail |
| 0x0010 | 0x0040 | DAC COMMON | See the DAC Common table for more detail |
| 0x0080 | 0x0200 | DAC TPL | See the JESD TPL table for more detail |
| 0x0100 | 0x0400 | DAC CHANNELS | See the DAC Channel table for more detail |
| Address | Bits | Name | Type | Default | Description |
|---|---|---|---|---|---|
| DWORD | BYTE | ||||
| 0x0000 | 0x0000 | REG_VERSION | Version and Scratch Registers | ||
| [31:0] | VERSION[31:0] | RO | 0x00000000 | Version number. Unique to all cores. | |
| 0x0001 | 0x0004 | REG_ID | Version and Scratch Registers | ||
| [31:0] | ID[31:0] | RO | 0x00000000 | Instance identifier number. | |
| 0x0002 | 0x0008 | REG_SCRATCH | Version and Scratch Registers | ||
| [31:0] | SCRATCH[31:0] | RW | 0x00000000 | Scratch register. | |
| 0x0003 | 0x000c | REG_CONFIG | Version and Scratch Registers | ||
| [0] | IQCORRECTION_DISABLE | RO | 0x0 | If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance) | |
| [1] | DCFILTER_DISABLE | RO | 0x0 | If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance) | |
| [2] | DATAFORMAT_DISABLE | RO | 0x0 | If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance) | |
| [3] | USERPORTS_DISABLE | RO | 0x0 | If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance) | |
| [4] | MODE_1R1T | RO | 0x0 | If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet) | |
| [5] | DELAY_CONTROL_DISABLE | RO | 0x0 | If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance) | |
| [6] | DDS_DISABLE | RO | 0x0 | If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance) | |
| [7] | CMOS_OR_LVDS_N | RO | 0x0 | CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance) | |
| [8] | PPS_RECEIVER_ENABLE | RO | 0x0 | If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance) | |
| [9] | SCALECORRECTION_ONLY | RO | 0x0 | If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance) | |
| 0x0004 | 0x0010 | REG_PPS_IRQ_MASK | PPS Interrupt mask | ||
| [0] | PPS_IRQ_MASK | RW | 0x1 | Mask bit for the 1PPS receiver interrupt |
| Address | Bits | Name | Type | Default | Description |
|---|---|---|---|---|---|
| DWORD | BYTE | ||||
| 0x0010 | 0x0040 | REG_RSTN | DAC Interface Control & Status | ||
| [2] | CE_N | RW | 0x0 | Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables | |
| [1] | MMCM_RSTN | RW | 0x0 | MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. | |
| [0] | RSTN | RW | 0x0 | Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. | |
| 0x0011 | 0x0044 | REG_CNTRL_1 | DAC Interface Control & Status | ||
| [0] | SYNC | RW | 0x0 | Setting this bit synchronizes channels within a DAC, and across multiple instances. This bit self clears. | |
| 0x0012 | 0x0048 | REG_CNTRL_2 | DAC Interface Control & Status | ||
| [7] | PAR_TYPE | RW | 0x0 | Select parity even (0x0) or odd (0x1). | |
| [6] | PAR_ENB | RW | 0x0 | Select parity (0x1) or frame (0x0) mode. | |
| [5] | R1_MODE | RW | 0x0 | Select number of RF channels 1 (0x1) or 2 (0x0). | |
| [4] | DATA_FORMAT | RW | 0x0 | Select data format 2's complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1). | |
| [3:0] | RESERVED[3:0] | NA | 0x00 | Reserved | |
| 0x0013 | 0x004c | REG_RATECNTRL | DAC Interface Control & Status | ||
| [7:0] | RATE[7:0] | RW | 0x00 | The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock. | |
| 0x0014 | 0x0050 | REG_FRAME | DAC Interface Control & Status | ||
| [0] | FRAME | RW | 0x0 | The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1 DCI clock period) pulse on the interface. This bit self clears. | |
| 0x0015 | 0x0054 | REG_STATUS | DAC Interface Control & Status | ||
| [31:0] | CLK_FREQ[31:0] | RO | 0x00000000 | Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock. | |
| 0x0016 | 0x0058 | REG_STATUS | DAC Interface Control & Status | ||
| [31:0] | CLK_RATIO[31:0] | RO | 0x00000000 | Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr). | |
| 0x0017 | 0x005c | REG_STATUS | DAC Interface Control & Status | ||
| [0] | STATUS | RO | 0x0 | Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores. | |
| 0x0018 | 0x0060 | REG_DAC_CLKSEL | DAC Interface Control & Status | ||
| [0] | DAC_CLKSEL | RW | 0x0 | Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL | |
| 0x001C | 0x0070 | REG_DRP_CNTRL | DRP Control & Status | ||
| [28] | DRP_RWN | RW | 0x0 | DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). | |
| [27:16] | DRP_ADDRESS[11:0] | RW | 0x00 | DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). | |
| [15:0] | RESERVED[15:0] | RO | 0x0000 | Reserved for backwards compatibility | |
| 0x001D | 0x0074 | REG_DRP_STATUS | DAC Interface Control & Status | ||
| [17] | DRP_LOCKED | RO | 0x0 | If set indicates the MMCM/PLL is locked | |
| [16] | DRP_STATUS | RO | 0x0 | If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). | |
| [15:0] | RESERVED[15:0] | RO | 0x0000 | Reserved for backwards compatibility | |
| 0x001E | 0x0078 | REG_DRP_WDATA | DAC Interface Control & Status | ||
| [15:0] | DRP_WDATA[15:0] | RW | 0x0000 | DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). | |
| 0x001F | 0x007c | REG_DRP_RDATA | DAC Interface Control & Status | ||
| [15:0] | DRP_RDATA | RO | 0x0000 | DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). | |
| 0x0022 | 0x0088 | REG_UI_STATUS | User Interface Status | ||
| [1] | UI_OVF | RW1C | 0x0 | User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. | |
| [0] | UI_UNF | RW1C | 0x0 | User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. | |
| 0x0028 | 0x00a0 | REG_USR_CNTRL_1 | DAC User Control & Status | ||
| [7:0] | USR_CHANMAX[7:0] | RW | 0x00 | This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| 0x002E | 0x00b8 | REG_DAC_GPIO_IN | DAC GPIO inputs | ||
| [31:0] | DAC_GPIO_IN[31:0] | RO | 0x00000000 | This reads auxiliary GPI pins of the DAC core | |
| 0x002F | 0x00bc | REG_DAC_GPIO_OUT | DAC GPIO outputs | ||
| [31:0] | DAC_GPIO_OUT[31:0] | RW | 0x00000000 | This controls auxiliary GPO pins of the DAC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1). |
| Address | Bits | Name | Type | Default | Description |
|---|---|---|---|---|---|
| DWORD | BYTE | ||||
| 0x00000 | 0x0000 | REG_TPL_CNTRL | JESD, TPL Control | ||
| [3:0] | PROFILE_SEL | RW | 0x00 | Selects one of the available deframer/framers from the transport layer. Valid only if PROFILE_NUM > 1. | |
| 0x00001 | 0x0004 | REG_TPL_STATUS | JESD, TPL Status | ||
| [3:0] | PROFILE_NUM | RO | 0x00 | Number of supported framer/deframer profiles. | |
| 0x00010 | 0x0040 | REG_TPL_DESCRIPTOR_1 | JESD, TPL descriptor for profile | ||
| [7:0] | JESD_M | RO | 0x00 | Converter Count. | |
| [15:8] | JESD_L | RO | 0x00 | Lane Count. | |
| [23:16] | JESD_S | RO | 0x00 | Samples per Converter per Frame. | |
| [7:0] | JESD_F | RO | 0x00 | Octets per Frame per Lane. | |
| 0x00011 | 0x0044 | REG_TPL_DESCRIPTOR_2 | JESD, TPL descriptor for profile | ||
| [7:0] | JESD_N | RO | 0x00 | Converter Resolution. | |
| [15:8] | JESD_NP | RO | 0x00 | Total Number of Bits per Sample. | |
| 0x00012 | 0x0048 | REG_* | Profile 1, similar to registers 0x00010 to 0x00011. | ||
| 0x00014 | 0x0050 | REG_* | Profile 2, similar to registers 0x00010 to 0x00011. |
| Address | Bits | Name | Type | Default | Description |
|---|---|---|---|---|---|
| DWORD | BYTE | ||||
| 0x0000 | 0x0000 | REG_CHAN_CNTRL_1 | DAC Channel Control & Status (channel - 0) | ||
| [15:0] | DDS_SCALE_1[15:0] | RW | 0x0000 | The DDS scale for tone 1. Defines the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (channel_1_fullscale * scale_1) + (channel_2 * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1). | |
| 0x0001 | 0x0004 | REG_CHAN_CNTRL_2 | DAC Channel Control & Status (channel - 0) | ||
| [31:16] | DDS_INIT_1[15:0] | RW | 0x0000 | The DDS phase initialization for tone 1. Defines the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1). | |
| [15:0] | DDS_INCR_1[15:0] | RW | 0x0000 | Defines the resolution of the phase accumulator. Its value can be defined by INCR = (f_out * 2^16) * clkratio / f_if; where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1). | |
| 0x0002 | 0x0008 | REG_CHAN_CNTRL_3 | DAC Channel Control & Status (channel - 0) | ||
| [15:0] | DDS_SCALE_2[15:0] | RW | 0x0000 | The DDS scale for tone 1. Defines the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (channel_1_fullscale * scale_1) + (channel_2 * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1). | |
| 0x0003 | 0x000c | REG_CHAN_CNTRL_4 | DAC Channel Control & Status (channel - 0) | ||
| [31:16] | DDS_INIT_2[15:0] | RW | 0x0000 | The DDS phase initialization for tone 1. Defines the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1). | |
| [15:0] | DDS_INCR_2[15:0] | RW | 0x0000 | Defines the resolution of the phase accumulator. Its value can be defined by INCR = (f_out * 2^16) * clkratio / f_if; where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1). | |
| 0x0004 | 0x0010 | REG_CHAN_CNTRL_5 | DAC Channel Control & Status (channel - 0) | ||
| [31:16] | DDS_PATT_2[15:0] | RW | 0x0000 | The DDS data pattern for this channel. | |
| [15:0] | DDS_PATT_1[15:0] | RW | 0x0000 | The DDS data pattern for this channel. | |
| 0x0005 | 0x0014 | REG_CHAN_CNTRL_6 | DAC Channel Control & Status (channel - 0) | ||
| [2] | IQCOR_ENB | RW | 0x0 | if set, enables IQ correction. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1). | |
| [1] | DAC_LB_OWR | RW | 0x0 | If set, forces DAC_DDS_SEL to 0x8, loopback If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored | |
| [0] | DAC_PN_OWR | RW | 0x0 | IF set, forces DAC_DDS_SEL to 0x09, device specific pnX If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored | |
| 0x0006 | 0x0018 | REG_CHAN_CNTRL_7 | DAC Channel Control & Status (channel - 0) | ||
| [3:0] | DAC_DDS_SEL[3:0] | RW | 0x00 | Select internal data sources (available only if the DAC supports it). 0x00: internal tone (DDS) 0x01: pattern (SED) 0x02: input data (DMA) 0x03: 0x00 0x04: pn7 (standard O.150) 0x05: pn15 (standard O.150) 0x06: pn23 (standard O.150) 0x07: pn31 (standard O.150) 0x08: loopback data (ADC) 0x09: pnX (Device specific e.g. ad9361) | |
| 0x0007 | 0x001c | REG_CHAN_CNTRL_8 | DAC Channel Control & Status (channel - 0) | ||
| [31:16] | IQCOR_COEFF_1[15:0] | RW | 0x0000 | IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). | |
| [15:0] | IQCOR_COEFF_2[15:0] | RW | 0x0000 | IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). | |
| 0x0008 | 0x0020 | REG_USR_CNTRL_3 | DAC Channel Control & Status (channel - 0) | ||
| [25] | USR_DATATYPE_BE | RW | 0x0 | The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| [24] | USR_DATATYPE_SIGNED | RW | 0x0 | The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| [23:16] | USR_DATATYPE_SHIFT[7:0] | RW | 0x00 | The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| [15:8] | USR_DATATYPE_TOTAL_BITS[7:0] | RW | 0x00 | The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| [7:0] | USR_DATATYPE_BITS[7:0] | RW | 0x00 | The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| 0x0009 | 0x0024 | REG_USR_CNTRL_4 | DAC Channel Control & Status (channel - 0) | ||
| [31:16] | USR_INTERPOLATION_M[15:0] | RW | 0x0000 | This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| [15:0] | USR_INTERPOLATION_N[15:0] | RW | 0x0000 | This holds the user interpolation N value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). | |
| 0x000A | 0x0028 | REG_USR_CNTRL_5 | DAC Channel Control & Status (channel - 0) | ||
| [1:0] | DAC_IQ_MODE[1:0] | RW | 0x0 | Allows IQ swap | |
| 0x0010 | 0x0040 | REG_* | Channel 1, similar to registers 0x100 to 0x10f. | ||
| 0x0020 | 0x0080 | REG_* | Channel 2, similar to registers 0x100 to 0x10f. | ||
| 0x00F0 | 0x03c0 | REG_* | Channel 15, similar to registers 0x100 to 0x10f. |
The data is intended for the DAC can have multiple sources:
- DMA source Raw data can be accepted from a external block representing the Application layer.
- DDS source For each DAC channel a dual-tone can be generated by a DDS core.
- PRBS source For each DAC channel one of the following PN sequence can be selected: PN7, PN15, inverted PN7, inverted PN15
The application layer connects to the framer block when the DMA source is selected. The framer module takes sample data and maps it onto the format that the JESD204 link expects for the specified framer configuration.
The data in the application layer interface dac_ddata is expected to have the following layout:
MSB LSB
[ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ]
Where MjSi refers to the i-th sample of the j-th converter. With m being the number of converters and n the number of samples per converter per beat.
The core asserts the enable signal for each channel that is enabled by the software. The dac_ddata data bus must contain data for each channel regardless if the channels are enabled or not.
The link layer interface description can be found in the User Data Interface section of the JESD204B Link Transmit Peripheral IP.
The REG_STATUS (0x054) register CLK_FREQ field allows to determine the clock rate of the device clock (link_clk) relative to the AXI interface clock (s_axi_aclk). This can be used to verify that the device clock is running at the expected rate.
The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 indicates that the link clock is currently not active.
Reduced number of octets-per-frame (F) settings. The following values are supported by the peripheral: 1, 2, 4
To ensure correct operation it is highly recommended to use the Analog Devices provided JESD204B software packages for interfacing the peripheral. Analog Devices is not able to provide support in case issues arise from using custom low-level software for interfacing the peripheral.
Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the EngineerZone.
Return to JESD204B Interface Framework
Return to Arrow High-Speed Converter Platforms
| Information from this site was obtained from |  |