AD469x Platform FPGA Architecture axi_AD469x

axi_ad469x_if

The AD469x is a 16-channel, 16-bit, 1 MSPS/500kSPS, multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) that enables high performance data acquisition of multiple signals in a small form factor

The interface for the AD469x digital host is the _axi_ad469x_if _module in the Cyclone V FPGA. The block diagram is shown here:

This module receives one of 16 channels of conversion data from the AD469x at a time on the spi serial bus on sdi . This data is synchronous to sclk in the serial interface and is framed by the cnv signal positive edge. The cnv signal also acts as a trigger for data sampling internally in axi_ad469x_if. The cnv signal is generated by the axi_ad469x_if through an internal pulse counter logic which acts as a start of conversion for AD469x. The 24-bit serial data (MSB 16-bit ADC conversion data + LSB 8-bit status bits) from AD469x is collected and MSB 16-bit sign-extended conversion data is multiplexed into individual channel stream as per LSB 8-bit status bits. The conversion data from all the individual channel streams are then packed into 256-bit adc_data_packed.

Files

Name	Description
axi_ad469x_if.v	Verilog source
axi_ad469x_if_hw.tcl	Platform designer tcl file for AD469x IP subsystem

Interface parameters

Name	Description
ID	Setting ID to device module
NUM_OF_SDI	Number of sdi channel in ADC SPI bus for serial interface
NUM_OF_CHANNELS	Setting number of ADC data channels
ADC_RESOLUTION	Size of ADC data per sample for each channel
DATA_BUS	Data size for Data bus within axi_ad469x_if module

Interface Signals

Name	Description
S_AXI_ACLK	AXI bus clk signal for AXI interface of axi_AD469x
S_AXI_ARESETN	AXI bus active low reset signal for AXI interface of axi_AD469x
S_AXI	slave AXI bus interface of axi_AD469x
CNV	Output signal from FPGA to ADC indicating start of conversion
SCLK	Serial clock out from FPGA for SPI bus
CS_N	Active low chip select from FPGA for enabling ADC communication
SDO	Serial Data out from FPGA for SPI
SDI	Serial Data in for FPGA for SPI bus . NUM_OF_SDI parameter sets number of input serial data in channels
ADC_DATA_PACKED	ADC conversion DATA packed. ADC_RESOLUTION and NUM_OF_CHANNELS sets the width in this bus
ADC_EN_PACKED	Active high signal indicating valid ADC data on ADC_DATA bus for FIFO interface on dma
ADC_SYNC_PACKED	Active high syncing signal for FIFO interface on dma
IRQ	IRQ signal for processor from SPI engine integrated within axi_ad469x_if module. (refer block diagram below)
ENABLE_IN	Input signal from axi_adc_core to select the required channel on adc_data_packed
SPI_CLK	Clock source for SPI engine integrated within axi_ad469x_if module. (refer block diagram below)

Configuration register

Address		Name	Description
DWORD	BYTE
0x0404	0x0101	up_data_seq	tells axi_ad469x_if about the sequence of AD469x mux in standard sequence only. works when adc_data_mode is set 1
0x0408	0x0102	up_cnv_rate	Sets the timer for internal pulse counter
0x040C	0x0103	{adc_data_mode, up_cnv_en, up_resetn}	to enable internal pulse counter and output cnv pulse , adc_data_mode sets the data mode
0x041C	0x0107	CNV_PULSE_WIDTH	Sets the pulse width of cnv pulse
0x0410	0x0104	up_scratch;	scratch pad register

Interfaces

• SPI Engine
• UTIL CPACK
• UP_AXI

Theory of Operation

The data and control stream from the processor is received through the s-axi interface which is then simplified into a simple microprocessor bus through up_axi module. The microprocessor bus is shared by both the spi_engine module and the internal configuration registers of axi_ad469x_if module. A internal pulse counter generates a cnv periodically as set by the up_cnv_rate register. The cnv pulse width is adjusted by the CNV_PULSE_WIDTH register. This cnv pulse acts as a trigger signal for the spi_engine module.

The adc_data_mode sets the manner in which the ADC data is captured. Setting the adc_data_mode directly corresponds to a change in the output waveform seen on the IIO Oscilloscope as well. Only the Standard Sequencing mode is supported when the adc_data_mode is enabled. When the adc_data_mode is disabled, both Standard as well as the Advanced Sequencing Modes are supported. The ADC data is then demultiplexed into respective channels by the channel ID present in the first four bits of the status bits appended with the incoming ADC data. Hence, for proper operation the STATUS_EN bit in the setup register 0x20 must be set to 1 in the AD469x internal register configuration (for details refer datasheet).

When adc_data_mode is enabled the FPGA Logic receives ADC data and then demultiplexes and buffers into respective channels by the channel ID, Likewise it will buffer other channels data till all the selected channel (in standard sequencing) is received while non selected channel data is kept 0. Once all channels data is received it is packed into 256bit adc_en_packed and send to DMA for memory transfer. When adc_data_mode is disabled FPGA Logic receives ADC data and simultaneously demultiplexes and transfer into respective channels by the channel ID, while other channels data is kept at its last value. Then data is packed in 256bit adc_en_packed and send to DMA for memory transfer. So when adc_data_mode is disabled each channel data retain its last value till the system is reset or receives updated data from ADC and this causes staggering of data on output waveform in IIOscope for this mode.

ADC DATA interface

The required channel is enabled by using the enable_in signal. The ADC data from the enabled channel adc_data_packed is packed in 256bit data width by a cpack module. The data size is set by the NUM_OF_CHANNEL and ADC_RESOLUTION parameters. The signals adc_en_packed and adc_sync_packed are generated along with the ADC data, which act as valid and sync signals respectively for FIFO interface of DMA module.

AD469x interface

The AD469x SPI bus is controlled and driven by SPI Engine module from FPGA. Internally SPI Engine takes the spi command stream and data from processor via up_axi module and Process and execute command stream and data in spi format. This initiates a communication to and fro with the AD469x. SPI Engine is used for register read and write operations within AD469x. There is an sub block called offload engine in SPI Engine which automates ADC conversion data read operation, whenever an external trigger signal like trigger_s is given to its trigger input. The 24bit ADC data ( 8 bits of status bits appended to the 16 bit data for each available channel )(for details refer datasheet) from AD469x is collected by offload engine and then bypassed from main bus as offload_sdi_data along with a valid and ready signal to a demux block. The demux block demuxes a 16 bit parallel data output for each channel using 8bits of status bits, ans send to the cpack module along with an adc_valid signal.

Note: This design is supported for only single SDO mode of AD469x.

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