AD469x configuration from IIOscope

Introduction

The AD469x is a 16-channel, 16-bit, 500 kSPS/1 MSPS, multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) which send adc data over serial peripheral (SPI) bus. The multiplexed data from 16 channel of AD469x is send in automated progression through a preprogrammed channel sequence, which can be configured by respective configuration register in AD469x. There are two types of sequence control in AD469x , one is standard sequencer control which automates progression through a preprogrammed set of enabled channels and advances through each enabled channel in ascending order and repeats the sequence until the device exits conversion mode. Other sequencing mode is the advanced sequencer which automates progression through a preprogrammed channel sequence where the order of channels is completely customizable. The advanced sequencer steps through a set of channel slots, where each slot can be assigned to any of the 16 analog inputs and sequences can be between two and 128 slots. The sequence progresses through the enabled slots in ascending order starting from Slot 0, and the sequence is repeated until the device exits conversion mode.

Both the sequencing modes are supported by EVAL-AD469x-FMCZ system design on DataStormDAQ. These two mode can be configured and result can be show on IIOscope which is described in below. Before changing any configuration from IIOscope kindly refer the AD469x datasheet.

Configuring AD469x from local IIO Oscilloscope.

A read write operation on any configuration register of AD469x can be done from local IIOscope. For this Power up the unit using this hardware configuration. Wait approximately 60 seconds for the unit to be fully functional.

Select axi_ad469x_adc device

From IIOscope main window , under a device selection section select select axi_ad469x_adc option from device drop dowm menu. After selection required option for Register map setting will be enabled, under source tab select SPI option.

Read/Write AD469x register

Now in Register map setting, there are two user input section , Address which is used to input required register address and other is value which take input for write operation or shows output in read operation on register. The Read tab is used for sending a read operation on the input address and value will be displayed in value section. Similarly write tab writes a value on entered address in address section. Enter the data in address and value section in hexadecimal format. Equivalent decimal value will be shown beside each section.

Note: Kindly avoid using Register map setting during ADC data capture on capture widow of IIOscope. It will halt the reading operation.

The address of data register can be referred from product datasheet. There two sets of register in AD469x , single byte and multibyte registers. IIoscope supports both types of register access.

Note : For multibyte register access kindly enter address + 1, from datasheet in address section of IIOscope to have 16byte read/write operation. Accessing multibyte register on same address from datasheet will be operation corresponding to LSB single byte.

Note : Additionally for data mode configuration, a address 0X0400 (data_mode_register) can be accessed from IIOscope . This address is internal to FPGA hdl design for AD469x. For detail you can refer FPGA architecture design page of AD469x.

Configuring sequencing mode

Note : HDL design for AD469x is based on single SDO mode and status bit enabled in ADC data. Also register access setting is kept on single cycle multibyte access. So kindly ensure this configuration setting are not altered in AD469x. Ensure below setting are kept as it is in AD469x, altering it will result in design to function incorrectly.

Register Address	Bit Number	Description	value
0x001	3	ADDR_LEN	0
0x010	5	MB_STRICT	1
0x020	5	STATUS_EN	1
0x020	4	LDO_EN	1
0x023	0	AC_EN	0
0x027	3:2	SDO_MODE	3

The AD469x can be configured in one of this sequencing mode as follows

Standard sequencing mode

Standard sequencing mode can be configured by setting STD_SEQ_EN bit in STD_SEQ_CTRL register (0x022). This will make AD469x to automates progression through a preprogrammed set of enabled channels in ascending order. This required channels can be enabled by setting bits in STD_SEQ_CONFIG register, where each bit corresponds to respective channel number. For selecting channel and writing STD_SEQ_CONFIG register address 0x025 need to be accessed for multibyte write.

Advanced sequencing mode

Advanced sequencing mode can be configured by clearing STD_SEQ_EN bit in STD_SEQ_CTRL register (0x022). This will make AD469x to automates progression through a preprogrammed customizable channel sequence and steps through a set of channel slots, where each slot can be assigned to any of the 16 analog inputs and sequences can be between two and 128 slots. Value written in NUM_SLOTS_AS bit of STD_SEQ_CONFIG register will set a number of slots in one progression cycle. Register address 0x100 (AS_SLOTn) onwards corresponds to slot number n among 128 slots sequentially and respectively. Value written in SLOT_INX bits of these register allots channel number corresponding to bit value in corresponding slot. Similarly Advanced sequencing mode will progress from channel number in each selected slots in one progression cycle.

ADC data_mode in HDL

data_mode bit (bit no 0 at address 0x400) in IIOscope will configure this design to sample data in step mode or continuous mode. This configuration is internal to FPGA HDL design. Setting data_mode bit 1 make data sampling in continuous mode. Internal HDL design will collect and buffer ADC data till all enable channel data is received in one progression cycle, then it will send buffered data collectively to dma. Output on IIOscope will be a continuous waveform. User must select the Enabled channel from STD_SEQ_CONFIG only on IIOscope, selecting disabled channel will give output value as 0xDEAD from the corresponding channel on IIOscope.

Note : Only Standard sequencing mode is supported when data_mode is set to 0. Bit value of STD_SEQ_EN will be overwrite to 1 in STD_SEQ_CTRL register (0x022) by the AD469x device driver. Also the effective frequency in continuous mode is increased due to skippage of time units

Clearing data_mode bit to 0 make data sampling in step and staggered manner. Internal HDL design will collect and send data directly to dma and will not wait for progression cycle to complete. Next value of respective channel will be updated in its next sequence only. So Output on IIOscope will be a a step and staggered manner. The length of step will depend on the number on other channel sequence between a selected channel. User must select the enabled channel only on IIOscope, selecting disabled channel will give any last state value from the corresponding channel.

Note : For data_mode is bit to 0, both standard and advanced sequencing mode is supported. User need to configure either of mode in AD469x for displaying data on IIOscope.

For advance sequence, the data from a selected channel at particular sampling instance is updated in DMA whereas other channels data is kept at last value till the next muxing of particular channel. So this adds some fixed steps in output on IIOscope , which adds noise in FFT plot for that channel. To get proper FFT and waveform it is advisable to enable only one required channel in a slot in AS_SLOTn.
Whereas in standard sequence with data_mode bit to 1 , the selected channel data is buffered till all the selected data channel is sampled , then it is moved to DMA so as to have continuous waveform on IIOscope. But this make FFT frequency for input signal time the factor depending on number of channel enabled in STD_SEQ_CTRL register. So it is advisable to use Standard sequence with only one required channel enables for proper FFT plot and waveform on IIOscope.

Note : By default design has data_mode bit to 0 (staggered mode) with only channel 0 enabled in standard sequencer mode.

Return to Run the Demonstration Standalone (AD469x)