AD7606B Platform FPGA Architecture SPI Engine Interconnect Module

SPI Engine Interconnect FPGA Peripheral

The SPI Engine Interconnect module allows connecting multiple SPI Engine Control Interface masters to a single SPI Engine Control Interface slave. This enables multiple command stream generators to connect to a single [SPI Engine Execution module][2] and consequential give them access to the same SPI bus. The interconnect modules take care of properly arbitrating between the different command streams.

Combining multiple command stream generators in a design and connecting them to a single execution module allows for the creation of flexible and efficient designs using standard components.

Files

Name	Description
spi_engine_interconnect.v	Verilog source for the peripheral.
spi_engine_interconnect_v1_0_hw.tcl	TCL script to generate Platform Designer IP

Configuration Parameters

Name	Description	Default
DATA_WIDTH	Data width of the parallel SDI/SDO data interfaces.	8
NUM_OF_SDI	Number of SDI lines on the physical SPI interface.	1

Signal and Interface Pins

Name	Type	Description
clk	Clock	A signals of the module are synchronous to this clock.
resetn	Synchronous active-low reset	Resets the internal state of the module.
s0_ctrl	SPI Engine Control Interface slave	Connects to the first control interface master
s1_ctrl	SPI Engine Control Interface slave	Connects to the second control interface master
m_ctrl	SPI Engine Control Interface master	Connects to the control interface slave

Theory of Operation

The SPI Engine Interconnect module has multiple SPI Engine Control Interface slave ports and a single SPI Engine Control Interface master port. It can be used to connect multiple command stream generators to a single command execution engine. Arbitration between the streams is done on a priority basis, streams with a lower index have higher priority. This means if commands are present on two streams arbitration will be granted to the one with the lower index. Once arbitration has been granted the port it was granted to stays in control until it sends a SYNC command. When the interconnect module sees a SYNC command arbitration will be re-evaluated after the SYNC command has been completed. This makes sure that once a SPI transaction consisting of multiple commands has been started it is able to complete without being interrupted by a higher priority stream.

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