GSRD Compile Hardware Design

Under construction

Compile Hardware Design

Overview

This page demonstrates how to compile the FPGA Hardware design that is delivered as part of the GSRD release.

The compilation will produce the following items:

File	Description
.sof	SRAM Object File - FPGA programming file, resulted from compiling the FPGA hardware project
.sopcinfo	SOPC Info File - containing a description of the hardware to be used by Device Tree Generator
.svd	System View Description File - describes the hardware for the Intel debugger
Handoff	Folder containing a description of the hardware to be used by the Preloader Generator

Steps to build the design

1. Acquiring top-level files
2. Creating project framework
3. Creating Processor System
4. Adding display IP
5. Making connections in Platform Builder
6. Creating top-level design

Return to Building the GHRD

Return to DataStorm DAQ GSRD Documentation

Return to Platform Table of Contents