AD7606B Platform FPGA Architecture axi_ad7616_pif

The axi_ad7616_pif module controls parallel interface of AD7606B. It generates active low chip select signal cs_n, read enable rd_n and write enable wr_n signal. db_t signal controls the direction of parallel bidirectional data bus db signal where db_i is 16-bit input and db_o is 16 bit output. It receives 16-bit parallel data from ADC and converts it to adc_data signal with adc_sync and adc_valid signal for interfacing with dma fifo interface. here adc_data is 16-bit wide means AD7606B 8-channel data are buffered sequentially. wr_req and rd_req signal from control block act as precursor to generate wr_n and rd_n signal and wr_data and rd_data for flow of data between FPGA and ADC in register read/ write functionality. end_of_conv is negative edge of trigger_s signal from control block which trigger adc data capturing from AD7606B. adc_data_chx is 16-bit parallel data of each 8-channel arrange for PACK module with adc_valid_pp signal.

Files

Name	Description
axi_ad7616_pif.v	Verilog source

Interface parameters

Name	Description
ADC_RESOLUTION	Sets the data width of parallel interface bus db
NUM_OF_CHANNELS	Sets the number of channels to capture from ADC

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