AD7606B Platform FPGA Architecture SPI Engine

AD7606B Platform SPI Engine Architecture

The Module allow the axi_ad7606b to receive data in the FPGA from the AD7606B ADC using a serial SPI interface over the FMC LPC connector.

SPI Engine

SPI Engine is a highly flexible and powerful SPI controller framework. It consists of multiple sub-modules which communicate over well-defined interfaces. This allows a high degree of flexibility and re-usability, while at the same time staying highly customizable and easily extensible.

The core component of the SPI Engine framework is a lean but powerful fully-programmable execution module, which implements the SPI bus-control logic. The SPI Engine execution module is controlled by a command stream which is generated by a separate module. Different command stream master modules are available and can be used depending on the system requirements. For example, a software-controlled memory-mapped command stream offers high flexibility, while an offload core, which executes a pre-programmed command stream when triggered by an external event (in this case drdy pulse from ad7768-1), allows for very low latency response times. By using a SPI Engine interconnect it is possible to connect multiple command stream master modules to a SPI Engine execution module.

Sub-modules

from right to left

• SPI Engine Execution Module:  Main module that processes a SPI engine command stream and implements the SPI bus interface logic
• SPI Engine Interconnect Module:  Connects multiple SPI Engine command streams to a SPI Engine execution module
• SPI Engine Offload Module:  Stores a SPI Engine command stream; execution is triggered by an external event
• AXI SPI Engine Module:  Memory-mapped software-accessible interface to a SPI Engine command stream and/or offload cores

Additional Documents

• Presentation: SPI Engine Design Philosophy

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