Add SPI Engine IP

Open the Platform Designer project

• Open a shell (Ctrl+Alt+T)

• Open Quartus® 20.1

    $ ~/intelFPGA_lite/20.1/quartus/bin/quartus &
  

• Open the Project

    File --> Open Project
  
    Navigate to /home/soceds/datastorm_daq/hdl/projects/arrow_ghrd/tei0022/partial_source/system_top.qpf
  

• Open the project in Platform Designer

    Tools --> Platform Designer
  
    Select system_bd.qsys and press Open
  

Add spi_engine_pll

• Find the PLL Intel FPGA IP in the IP Catalog,
• Double click it to add it to the System Contents.
• In the wizard, confirm or update the following settings:
  • In the General tab, set the Reference Clock Frequency to 100.0 MHz,
  • Check the Enable locked output port,
  • Change the outclk0 Desired Frequency to 166.667 MHz,
  • Click Finish.

• Rename it spi_engine_pll.
• Connect the spi_engine_pll.refclk port to the sys_hps.h2f_user1_clock spine.
• Connect the spi_engine_pll.reset port to the sys_clk.clk_reset spine.
• spi_engine_pll.outclk0 will be connected later.

Add spi_engine_execution

• Find the spi_engine_execution_v1_0 IP in the IP Catalog,
• Double click it to add it to the System Contents.
• In the wizard, make the following settings:
  • NUM_OF_CS: = 1,
  • DEFAILT_SPI_CFG: = 0,
  • DEFAULT_CLK_DIV: = 0,
  • DATA_WIDTH: = 20,
  • NUM_OF_SDI: = 1,
  • SDO_DWFAULT: = 0x1,
  • SDI_DELAY: = 0x2.
• Click Finish.

• Rename it spi_engine_execution_0.
• Connect the spi_engine_execution_0.clk port to the spi_engine_pll.outclk0 port.
• Double-click the Export column of the spi port and name it spi_engine_execution_0_spi_out.
• More connections will be made later.

Add spi_engine_interconnect

• Find the spi_engine_interconnect_v1_0 IP in the IP Catalog,
• Double click it to add it to the System Contents.
• In the wizard, make the following settings:
  • DATA_WIDTH: = 20,
  • NUM_OF_SDI: = 1,
• Click Finish.

• Rename it spi_engine_interconnect_0.
• Connect the spi_engine_interconnect_0.clk port to the spi_engine_pll.outclk0 port.
• connect the spi_engine_interconnect_0.m_ctrl port to the spi_engine_execution_0.ctrl port. (In addition to clicking on the node of the spi_engine_interconnect_0.m_ctrl port you must return to the spi_engine_execution_0 component to click on the node of the ctrl port as well.)
• More connections will be made later.

Add spi_engine_offload

• Find the spi_engine_offload_v1_0 IP in the IP Catalog,
• Double click it to add it to the System Contents.
• In the wizard, make the following settings:
  • ASYNC_SPI_CLK: = 1,
  • ASYNC_TRIG: = 0,
  • CMD_MEM_ADDRESS_WIDTH: = 4,
  • SDO_MEM_ADDRESS_WIDTH: = 4,
  • DATA_WIDTH: = 20,
  • NUM_OF_SDI: = 1.
• Click Finish.

• Rename it spi_engine_offload_0.
• Connect the spi_engine_offload_0.ctrl_clk and spi_clk ports to the spi_engine_pll.outclk0 port.
• connect the spi_engine_offload_0.spi_engine_ctrl port to the spi_engine_interconnect_0.s0_ctrl port.
• More connections will be made later.

Add axi_spi_engine

• Find the axi_spi_engine_v1_0 IP in the IP Catalog,
• Double click it to add it to the System Contents.
• In the wizard, make the following settings:
  • CMD_FIFO_ADDRESS_WIDTH: = 4,
  • SYNC_FIFO_ADDRESS_WIDTH: = 4,
  • SDO_FIFO_ADDRESS_WIDTH: = 5,
  • SDI_FIFO_ADDRESS_WIDTH: = 5,
  • MM_IF_TYPE: = 0,
  • ASYNC_SPI_CLK: = 1,
  • NUM_OFFLOAD: = 1,
  • OFFLOAD0_CMD_MEM_ADDRESS_WIDTH: = 4,
  • OFFLOAD0_SDO_MEM_ADDRESS_WIDTH: = 4,
  • ID: = 0,
  • DATA_WIDTH: = 20,
  • NUM_OF_SDI: = 1.
• Click Finish.

• Rename it axi_spi_engine_0.
• Connect the axi_spi_engine_0.s_axi_aclk port to the sys_hps.h2f_user1_clock spine.
• Connect the axi_spi_engine_0.s_axi_aresetn port to the sys_clk.clk_reset spine.
• connect the axi_spi_engine_0.spi_engine_ctrl port to the spi_engine_interconnect_0.s1_ctrl port.
• connect the axi_spi_engine_0.spi_engine_offload_ctrl0 port to the spi_engine_offload_0.spi_engine_offload_ctrl port.
• connect the axi_spi_engine_0.s_axi port to the sys_hps.h2f_lw_axi_master port.
• Connect the axi_spi_engine_0.spi_clk port to the spi_engine_pll.outclk0 port.
• Connect the axi_spi_engine_0.irq port to both the sys_hps.f2h_irq0 and sys_hps.f2h_irq1 ports.
• More connections will be made later.

Add spi_dmac

• Find the axi_dmac in the Analog Devices Library of the IP Catalog,
• Double click it to add it to the System Contents,
• In the wizard, make the following settings and click Finish:
  • Change the Source Type to Streaming AXI, 32-bit,
  • Change the Destination Type to Memory-Mapped AXI, 64-bit, and Check the Insert Register Slice box,
  • Un-check all Features boxes ,
  • Click Finish.

• Rename it spi_dmac_0.
• Connect the spi_dmac_0.s_axi_clock and spi_dmac_0.m_dest_axi_clock ports to the sys_hps.h2f_user1_clock port.
• Connect the spi_dmac_0.s_axi_reset, and spi_dmac_0.m_dest_axi_reset ports to the sys_clk.clk_reset spine.
• Connect the spi_dmac_0.s_axi bus to the sys_hps.h2f_lw_axi_master port.
• Connect the spi_dmac_0.if_s_axis_aclk ports to the spi_engine_pll.outclk0 port.
• Connect the spi_dmac_0.interrupt_sender port to both the sys_hps.f2h_irq0 and sys_hps.f2h_irq1 ports.
• Connect the spi_dmac_0.m_dest_axi port to the sys_hps.f2h_sdram1_data port,
• More connections will be made later.

Add upscale_converter

• Find the util_axis_upscale_v1_0 in the Analog Devices Library of the IP Catalog,
• Double click it to add it to the System Contents,
• In the wizard, make the following settings:
  • NUM_OF_CHANNELS: = 1,
  • DATA_WIDTH: = 24,
  • UDATA_WIDTH: = 32.
  • Click Finish.

• Rename it upscale_converter_0.
• Connect the upscale_converter_0.s_axis bus to the spi_engine_offload_0.offload_sdi port.
• Connect the upscale_converter_0.clk port to the spi_engine_pll.outclk0 port.
• Connect the upscale_converter_0.m_axis port to the spi_dmac_0.s_axis port.
• Double-click in the export column of the dfmt_enable port and name it upscale_converter_0_dfmt_enable,
• Double-click in the export column of the dfmt_type port and name it upscale_converter_0_dfmt_type,
• Double-click in the export column of the dfmt_se port and name it upscale_converter_0_dfmt_se,
• More connections will be made later.

Add trigger_gen

• Find the util_pulse_gen_v1_0 in the Analog Devices Library of the IP Catalog,
• Double click it to add it to the System Contents,
• In the wizard, make the following settings:
  • PULSE_PERIOD: = 93,
  • PULSE_WIDTH: = 1,
  • Click Finish.

• Rename it trigger_gen_0.
• Connect the trigger_gen_0.clk port to the spi_engine_pll.outclk0 port.
• Connect the trigger_gen_0.pulse port to the spi_engine_offload_0.trigger port.
• Double-click in the export column of the pulse_width port and name it trigger_gen_0_pulse_width,
• Double-click in the export column of the pulse_period port and name it trigger_gen_0_pulse_period,
• Double-click in the export column of the load_config port and name it trigger_gen_0_load_config,
• More connections will be made later.

Complete Connections and set Base Addresses

• Connect axi_spi_engine_0.spi_resetn port to spi_engine_offload_0.spi_resetn, spi_engine_interconnect_0.resetn, spi_engine_execution_0.resetn, upscale_converter_0.resetn, and trigger_gen_0.rstn ports,

• Set the axi_spi_engine_0 Base Address to 0x0004_0000 and lock it,

• Set the axi_spi_engine_0 IRQ number to 6,

• Set the spi_dmac_0 Base Address to 0x0005_0000 and lock it,

• Set the spi_dmac_0 IRQ number to 5,

Conclude settings in Platform Designer

If there are no messages in red color, do:

• Click the Generate HDL button in the bottom right of the window,
• Click Generate in the Generation window that pops up,
• Click Close in the Save System window,
• Click Close when the Generate window finishes.
• Optionally, close the Platform Designer by clicking Finish.

Next - Modify Top Level HDL

Return to Modify GHRD