AD7606B Platform FPGA Architecture SPI Engine AXI Interface Module

AXI SPI Engine FPGA Peripheral

The AXI SPI Engine peripheral allows asynchronous interrupt-driven memory-mapped access to a SPI Engine Control Interface. This is typically used in combination with a software program to dynamically generate SPI transactions.

The peripheral has also support for providing memory-mapped access to one or more offload cores and changes its content dynamically at runtime.

Files

Name	Description
axi_spi_engine.v	Verilog source for the peripheral.
axi_spi_engine_hw.tcl	TCL script to generate the Quartus Prime Platform Designer project for the peripheral.

Configuration Parameters

Name	Description	Default
ASYNC_SPI_CLK	If set to 1 the s_axi_aclk and spi_clk clocks are assumed to be asynchronous.	1
CMD_FIFO_ADDRESS_WIDTH	Configures the size of the command FIFO.	4
SDO_FIFO_ADDRESS_WIDTH	Configures the size of the serial-data out FIFO.	5
SDI_FIFO_ADDRESS_WIDTH	Configures the size of the serial-data in FIFO.	5
NUM_OFFLOAD	The number of offload control interfaces	0

Signal and Interface Pins

Name	Type	Description
s_axi_aclk	Clock	All s_axi signals and irq are synchronous to this clock.
s_axi_aresetn	Synchronous active-low reset	Resets the internal state of the peripheral.
s_axi	AXI-Lite bus slave	Memory-mapped AXI-lite bus that provides access to modules register map.
irq	Level-High Interrupt	Interrupt output of the module. Is asserted when at least one of the modules interrupt is pending and unmasked.
spi_clk	Clock	All spi_engine_ctrl signals and spi_resetn are synchronous to this clock.
spi_engine_ctrl	SPI Engine Control Interface slave	SPI Engine Control stream that contains commands and data for the execution module.
spi_resetn	Output	This signal is asserted when the module is disabled through the ENABLE register. Typically used as the reset for the SPI Engine modules connected to these modules.

Register Map

SPI Engine (axi_spi_engine)

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Address		Register	Bits	Name	Type	Default	Description
DWORD	BYTE
0x00	0x0000	VERSION	[31:16]	VERSION_MAJOR	RO	0x01	Version of the peripheral. Follows semantic version. Current version 1.00.71
			[15:0]	VERSION_MINOR	RO	0x00
			[7:0]	VERSION_PATCH	RO	0x71
0x01	0x0004	PERIPHERAL_ID	[31:0]	PERIPHERAL_ID	RO	ID	Value of the ID configuration parameter. In case of multiple instances, each instance will have a unique ID
0x02	0x0008	SCRATCH	[31:0]	SCRATCH	RW	0x00000000	Scratch register useful for debug
0x03	0x000c	DATA_WIDTH	[31:0]	DATA_WIDTH	RO	0x00000008	Data width fo the SDI/SDO parallel interface. It is equal to the max supported transfer length in bits
0x10	0x0040	ENABLE	[31:0]	ENABLE	RW	0x00000001	Enable register. If the enable bit is set to 1 the internal state of the peripheral is reset. For proper operation, the bit needs to be set to 0.
0x20	0x0080	IRQ_MASK	[0]	CMD_ALMOST_EMPTY	RW	0x0	If set to 0 the CMD_ALMOST_EMPTY interrupt is masked.
			[1]	SDO_ALMOST_EMPTY	RW	0x0	If set to 0 the SDO_ALMOST_EMPTY interrupt is masked.
			[2]	SDI_ALMOST_FULL	RW	0x0	If set to 0 the SDI_ALMOST_EMPTY interrupt is masked.
			[3]	SYNC_EVENT	RW	0x0	If set to 0 the SYNC_EVENT interrupt is masked.
0x21	0x0084	IRQ_PENDING	[31:0]	IRQ_PENDING	RW1C	0x00000000	Pending IRQs with mask.
0x22	0x0088	IRQ_SOURCE	[31:0]	IRQ_SOURCE	RO	0x00000000	Pending IRQs without mask.
0x30	0x00c0	SYNC_ID	[31:0]	SYNC_ID	RO	0x00000000	Last synchronization event ID received from the SPI Engine control interface.
0x34	0x00d0	CMD_FIFO_ROOM	[31:0]	CMD_FIFO_ROOM	RO	0x????????	Number of free entries in the command FIFO. The reset value of the CMD_FIFO_ROOM register depends on the setting of the CMD_FIFO_ADDRESS_WIDTH parameter.
0x35	0x00d4	SDO_FIFO_ROOM	[31:0]	SDO_FIFO_ROOM	RO	0x????????	Number of free entries in the serial-data-out FIFO. The reset value of the SDO_FIFO_ROOM register depends on the setting of the SDO_FIFO_ADDRESS_WIDTH parameter.
0x36	0x00d8	SDO_FIFO_LEVEL	[31:0]	SDO_FIFO_LEVEL	RO	0x????????	Number of valid entries in the serial-data-out FIFO.
0x38	0x00e0	CMD_FIFO	[31:0]	CMD_FIFO	WO	0x????????	Command FIFO register. Writing to this register inserts an entry into the command FIFO. Writing to this register when the command FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
0x39	0x00e4	SDO_FIFO	[31:0]	SDO_FIFO	WO	0x????????	SDO FIFO register. Writing to this register inserts an entry into the SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
0x3a	0x00e8	SDI_FIFO	[31:0]	SDI_FIFO	RO	0x????????	SDI FIFO register. Reading from this register removes the first entry from the SDI FIFO. Reading this register when the SDI FIFO is empty will return undefined data. Writing to it has no effect.
0x3c	0x00f0	SDI_FIFO_PEEK	[31:0]	SDI_FIFO_PEEK	RO	0x????????	SDI FIFO peek register. Reading from this register returns the first entry from the SDI FIFO, but without removing it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined data. Writing to it has no effect.
0x40	0x0100	OFFLOAD0_EN	[31:0]	OFFLOAD0_EN	RW	0x00000000	Set this bit to enable the offload module.
0x41	0x0104	OFFLOAD0_STATUS	[31:0]	OFFLOAD0_STATUS	RO	0x00000000	Offload status register.
0x42	0x0108	OFFLOAD0_MEM_RESET	[31:0]	OFFLOAD0_MEM_RESET	WO	0x00000000	Resets the memory of the offload module.
0x44	0x0110	OFFLOAD0_CDM_FIFO	[31:0]	OFFLOAD0_CDM_FIFO	WO	0x????????	Offload command FIFO register. Writing to this register inserts an entry into the command FIFO of the offload module. Writing to this register when the command FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
0x45	0x0114	OFFLOAD0_SDO_FIFO	[31:0]	OFFLOAD0_SDO_FIFO	WO	0x????????	Offload SDO FIFO register. Writing to this register inserts an entry into the offload SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
0x48	0x0120	PULSE_GEN_PERIOD	[31:0]	PULSE_GEN_PERIOD	RW	0x00000000	Output register for pulse generation period. Can be configured from software.

Access Type	Name	Description
RO	Read-only	Reads will return the current register value. Writes have no effect.
RW	Read-write	Reads will return the current register value. Writes will change the current register value.
WO	Write-only	Writes will change the current register value. Reads have no effect.
RW1C	Write-1-to-clear	Reads will return the current register value. Writing the register will clear those bits of the register which were set to 1 in the value written. Bits are set by hardware.

Theory of Operation

Typically a software application running on a CPU will be able to execute much faster than the SPI Engine command will be processed. In order to allow the software to execute other tasks while the SPI Engine is busy processing commands, the AXI SPI Engine peripheral offers interrupt-driven notification which can be used to notify the software when a SPI command has been executed. In order to reduce the necessary context switches, the AXI SPI Engine peripheral incorporates FIFOs to buffer the command as well as the data streams.

FIFOs

The AXI SPI Engine peripheral has three FIFOs, one for each of the command, SDO and SDI streams. The size of the FIFOs can be configured by setting the CMD_FIFO_ADDRESS_WIDTH, SDO_FIFO_ADDRESS_WIDTH and SDI_FIFO_ADDRESS_WIDTH parameters.

One end of the FIFOs are connected to a memory-mapped register and can be accessed via the AXI-Lite interface. The other end is directly connected to the matching stream of the SPI Engine Control interface

Data can be inserted into the command FIFO by writing to the CMD_FIFO register and new data can be inserted into the SDO_FIFO register. If an application attempts to write to a FIFO while the FIFO is already full, the data is discarded and the state of the FIFO remains unmodified. The number of empty entries in the command FIFO and SDO FIFO can be queried by reading the CMD_FIFO_ROOM or SDO_FIFO_ROOM register.

Data can be removed from the SDI FIFO by reading from the SDI_FIFO register. If an application attempts to read data while the FIFO is empty undefined data is returned and the state of the FIFO remains unmodified. It is possible to read the first entry in the SDI FIFO without removing it by reading from the SDI_FIFO_PEEK register. The number of valid entries in the SDI FIFO register can be queried by reading the SDI_FIFO_LEVEL register.

If the peripheral is disabled by setting the ENABLE register to 0, any data stored in the FIFOs is discarded and the state of the FIFO is reset.

Synchronization Events

Synchronization events can be used to notify the software application about the progress of the command stream. An application can insert a SYNC instruction at any point in the command stream. If the execution module reaches the SYNC instruction it will generate an event on the SYNC stream. When this event is received by the AXI SPI Engine peripheral it will update the SYNC_ID register with the received event ID and will assert the SYNC_EVENT interrupt.

Typically the SYNC instruction should be inserted after the last instruction in a SPI transaction. This will allow the application to be notified about the completion of the transaction and allows it to do further processing based on the result of the transaction.

It is recommended that synchronization IDs are generated in a monotonic incrementing or decrementing manner. This makes it possible to easily check if an event has completed by checking if it is less or equal (incrementing IDs) or more or equal (decrementing IDs) to the ID of the last completed event.

Interrupts

The SPI Engine AXI peripheral has 4 internal interrupts: One for each of the FIFOs which are asserted when the FIFO level falls bellow the almost empty level (for the command or SDO FIFO) or rises above the almost full level (for the SDI FIFO); and one interrupt which is asserted when a new synchronization event arrives. The peripheral has 1 external interrupt which is supposed to be connected to the upstream interrupt controller. The external interrupt is a logical OR-operation over the internal interrupts, meaning if at least one of the internal interrupts is asserted the external interrupt is asserted, and only if all internal interrupts are de-asserted the external interrupt is de-asserted. In addition, each interrupt has a mask bit which can be used to stop the propagation of the internal interrupt to the external interrupt. If an interrupt is masked it will count towards the external interrupt state as if it were not asserted. The mask bits can be modified by writing to the IRQ_MASK register. The raw interrupt status can be read from the IRQ_SOURCE register and the combined state of the IRQ_MASK and raw interrupt state can be read from the IRQ_PENDING register.

IRQ_PENDING = IRQ_SOURCE & IRQ_MASK; IRQ = |IRQ_PENDING;

FIFO Threshold Interrupts

The FIFO threshold interrupts can be used by software for flow control of the command, SDI and SDO streams. If an application wants to send more data than the FIFO can hold, the application can write samples into the FIFO until it is full, then suspend the operation and wait for the almost empty interrupt, and then continue writing data to the FIFO. Similarly, when the application wants to read more data than the FIFO can hold, it should listen for the almost full interrupt and read data from the FIFO when it occurs.

The FIFO threshold interrupt is asserted when then FIFO level rises above the watermark and is automatically de-asserted when the level drops below the watermark.

SYNC_EVENT Interrupt

The SYNC_EVENT interrupt is asserted when a new sync event is received from the sync stream. An application that generated a SYNC instruction on the command stream can use this interrupt to be notified when the sync instruction has been completed. To de-assert, the SYNC_EVENT interrupt the reception of the interrupt needs to be acknowledged by the application by writing a 1 to the SYNC_EVENT bit in the IRQ_PENDING register.

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